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w88227f/W88227QD atapi cd - rom decoder and up8032 draft rev. 0.7 h e a d q u a r t e r s n o . 4 , c r e a t i o n r d . i i i s c i e n c e - b a s e d i n d u s t r i a l p a r k h s i n c h u , t a i w a n t e l : 8 8 6 - 3 5 - 7 7 0 0 6 6 f a x : 8 8 6 - 3 5 - 7 8 9 4 6 7 w w w : h t t p : / / w w w . w i n b o n d . c o m . t w / t a i p e i o f f i c e 1 1 f , n o . 1 1 5 , s e c . 3 , m i n - s h e n g e a s t r d . t a i p e i , t a i w a n t e l : 8 8 6 - 2 - 7 1 9 0 5 0 5 f a x : 8 8 6 - 2 - 7 1 9 7 5 0 2 t l x : 1 6 4 8 5 w i n t p e w i n b o n d e l e c t r o n i c s ( h . k . ) l t d . r m . 8 0 3 , w o r l d t r a d e s q u a r e , t o w e r i i 1 2 3 h o i b u n r d . , k w u n t o n g k o w l o o n , h o n g k o n g t e l : 8 5 2 - 2 7 5 1 6 0 2 3 - 7 f a x : 8 5 2 - 2 7 5 5 2 0 6 4 w i n b o n d e l e c t r o n i c s ( n o r t h a m e r i c a ) c o r p . 2 7 3 0 o r c h a r d p a r k w a y s a n j o s e , c a 9 5 1 3 4 u . s . a . t e l : 1 - 4 0 8 - 9 4 3 6 6 6 6 f a x : 1 - 4 0 8 - 9 4 3 6 6 6 8 n o t e : a l l d a t a a n d s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t
w88227f/W88227QD data sheet revision history pages dates rev. version on web main contents 1 n/a 04/1999 0.40 first published, without dc/ac spec. 2 3, 8, 9, 12, 15, 34, 5 7, 63, 73, 75, 98 - 101 05/18/1999 0.50 with dc/ac spec. 3 12, 17, 18, 25, 26, 33, 42, 50, 60, 62, 86, 87 7/1999 0.60 erroneous content/figure fix 4 10/1/1999 0.70 add diagram of equivalent circuit add absolute maximum ratings add ac timing add ir re - f low profile remove application circuit add W88227QD package 5 6 7 8 9 10 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in th is datasheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
preliminary/confidential subject to change without notice w88227f - i - table of contents 1. overview 1 1.1 features 1 1.2 pin map 2 1.3 pin arrangement 4 1.4 basic configuration 8 2. functional descripti on 9 2.1 global function 9 2.1.1 decoder register access 9 2.1.2 reset source 9 2.1.3 clock source and power management 10 2.1.4 multi - function pins 11 2.1.4.1 gpio1/nfwe configuration 11 2.1.4.2 gpio2/daout/nfce configuration 11 2.1.4.3 gpio3/nccs1 configuration 11 2.1.4.4 gpio4/nccs2/ra8 configuration 12 2.1.4.5 up32/up33 configuration 12 2.1.4.6 asd/nroe configuration 12 2.1.4.7 cash/nwreh configuration 12 2.1.5 ide programming mode 13 2.1.5.1 pin mapping 13 2.1.5.2 ide programming sequence 13 2.1.5.3 initiation key 14 2.1.5.4 ide programming registers 14 2.1.6 power - on setting 15 2.1.7 external up (eup) mode 16 2.1.8 up test (upt) mode 16 2.2 d ecoder function 17 2.2.1 dram interface 17 2.2.1.1 memory layout 17 2.2.1.2 block configuration 18 2.2.1.3 linear transfer address count er 19 2.2.1.4 linear address v.s. block - offset address 20 2.2.2 microcontroller interface 21 2.2.2.1 programmable system clock 21 2.2.3 host interface 22 2.2.3.1 ultra dma mode setting 22 2.2.3.2 ultra dma error handling 22 2.2.3.3 ultra dma data - out 23 2.2.3.4 bsy flag c ontrol 24 2.2.3.5 pin hirq control 24
preliminary/confidential subject to change without notice w88227f - ii - 2.2.4 decoder logic 25 2.2.4.1 sync detection/insertion 25 2.2.4.2 descramble 25 2.2.4.3 disk - monitor mode 25 2.2.4.4 parallel ecc correction 25 2.2.4.5 edc checking 26 2.2.4.6 real time edc checking 26 2 .2.4.7 disc format selection 26 2.2.4.8 dsp main data format 26 2.2.4.9 cd - da data & q - channel extraction 27 2.2.4.10 target search 28 2 .2.4.11 automatic header comparison 28 2.2.4.12 status collection 28 2.2.4.13 buffer - independent - correction 28 2.2.4.14 remove frequent srib & automatic cache managem ent 28 2.2.5 audio - playback 31 2.2.5.1 configuration phase 31 2.2.5.2 playback phase 31 2.2.5.3 iec - 958 digital audio output 31 2.2.6 function differences between w88227 and w88113cf 32 2.2.7 decoder register map 33 2.3 up8032 function 93 2.3.1 data memory 93 2.3.2 ram and aux_ram 93 2.3.3 aux_rom mode and up programming flash 95 2.3.4 special function register (sfr) 95 3. diagram of equivalen t circuit in input/output port 99 4. electronic character istics 103 4.1 absolute maximum ratings 103 4.2 dc characteristics 103 4.3 ac characteristi cs 104 5. ordering instruction 109 6. how to read the top marking 109 7. package dimension 110 8. example temperature profile for infrar ed reflow 112
preliminary/confidential subject to change without notice w88227f/W88227QD - 1 - 1999/10/1 rev: 0.70 1. overview 1.1 features decoder t supports atapi cd - rom standard (sff 8020) t supports cd - rom, cd - rom/xa, cd - i, video - cd, photo - cd, cd - plus, and i - trax formats t supports drive speed up to 60 - fold t supports various types of dsps t supports various types of industry - standard drams (256k*16 ~ 64k*16, 256k*8, 128k*8) t supports real - time correction and buffer - independent - correction t supports automatic repeated error correction t 32 - byte fifo to improve ide interface throughput t support data transfer to host in pio, dma , and udma/66 mode t support block - offset - address - transfer and linear - address - transfer t support automatic atapi hardware macro t support automatic target header search and header comparison t support automatic cache buffer manag ement and transfer t support q - channel data extraction t support high - speed cav audio playback from dram buffer t support left and right channels routing and muting t support iec - 958 digital audio output t programmable system clock for decoder operation t support flas h programming through ide interface micro - controller t up to dc - 40mhz operation for built - in m p8032 t 512 bytes of on - chip scratchpad ram ( including 256 bytes re - addressable aux_ram) t aux_ram can also be dynamically programmed as an aux_rom ,which can be used as an internal rom to support flash programming by up t internal crystal loop off in power - d own mode to save more power t support programmable wake - up from power - down mode
preliminary/confidential subject to change without notice w88227f/W88227QD - 2 - 1999/10/1 rev: 0.70 miscellaneous t glue logic circuit saving (built - in 74373) t external rom/flash chip enable pin to save power in power - down mode t support hardware and firmware controlled reset out put t programmable decoder and servo chip - select base address t controllable clock output t multi - level power management t 128 - pin pqfp/ lqfp 1.2 pin map w88227f 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 2 1 0 1 0 1 0 1 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 gnd dxi dxo alrck abck asd/nroe lrck bck sdata c2po/sdata2 scsd wfck scsyn exck nrsto gpio1/nfwe gpio2/daout gpio3/nccs1 vdd uxi uxo cko npor up10 up11 up12 up13 nhrst up14 up15 up16 up17 up30 up31 up32/up33 up34 up35 up36 up26 up25 up24 up23 up22 up21 up20 a7 a6 a5 a4 a3 a2 a1 a0 psen up07 up06 up05 up04 gnd up03 up02 up01 up00 up37 gnd up27 ndasp ncs3 ncs1 da2 da0 npdiag da1 ncs16 ndmack hirq iordy nhrd nhwr dmarq dd15 dd0 dd14 dd1 vdd dd13 dd2 gnd dd12 dd3 dd11 dd4 dd10 dd5 dd9 dd6 rd15 dd7 dd8 rd0 rd14 rd1 rd13 rd2 rd12 rd3 gnd rd11 rd4 rd10 rd5 rd9 rd6 rd8 cas rd7 cash/nrweh nrwe ras gpio4/nccs2/ra8 ra7 ra0 ra6 ra1 ra5 ra2 ra4 ra3
preliminary/confidential subject to change without notice w88227f/W88227QD - 3 - 1999/10/1 rev: 0.70 W88227QD 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 6 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 64 63 62 61 60 59 9 4 6 9 6 8 6 7 6 6 7 3 7 2 7 1 7 0 7 6 7 5 7 4 7 7 8 1 8 0 7 9 7 8 8 5 8 4 8 3 8 2 8 9 8 8 8 7 8 6 9 3 9 2 9 1 9 0 9 6 9 5 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 97 98 99 100 101 102 gnd dxi dxo alrck abck asd/ nroe lrck bck sdata c2po/sdata2 scsd wfck scsyn exck nrsto gpio1/ nfwe gpio2/daout gpio3/nccs1 vdd uxi uxo cko npor up10 up11 up12 up13 nhrst up14 up15 up16 up17 up26 up25 up24 up23 up22 up21 up20 a7 a6 a5 a4 a3 a2 a1 a0 psen up07 up06 up05 up04 gnd up03 up02 up01 up00 up37 up35 up34 up32/up33 up31 up30 up36 gnd up27 ndasp ncs3 ncs1 da2 da0 npdiag da1 ncs16 ndmack hirq iordy nhrd nhwr dmarq dd15 dd0 dd14 dd1 vdd dd13 dd2 gnd dd12 dd3 dd11 dd4 dd10 dd5 dd9 dd6 rd13 rd2 rd12 rd3 gnd rd11 rd4 rd10 rd5 rd9 rd6 rd8 cas rd7 cash/ nrweh nrwe ras gpio4/nccs2/ra8 ra7 ra0 ra6 ra1 ra5 ra2 ra4 ra3 dd8 rd15 rd0 rd14 rd1 dd7 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 6 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 64 63 62 61 60 59 9 4 6 9 6 8 6 7 6 6 7 3 7 2 7 1 7 0 7 6 7 5 7 4 7 7 8 1 8 0 7 9 7 8 8 5 8 4 8 3 8 2 8 9 8 8 8 7 8 6 9 3 9 2 9 1 9 0 9 6 9 5 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 97 98 99 100 101 102 gnd dxi dxo alrck abck asd/ nroe lrck bck sdata c2po/sdata2 scsd wfck scsyn exck nrsto gpio1/ nfwe gpio2/daout gpio3/nccs1 vdd uxi uxo cko npor up10 up11 up12 up13 nhrst up14 up15 up16 up17 up26 up25 up24 up23 up22 up21 up20 a7 a6 a5 a4 a3 a2 a1 a0 psen up07 up06 up05 up04 gnd up03 up02 up01 up00 up37 up35 up34 up32/up33 up31 up30 up36 gnd up27 ndasp ncs3 ncs1 da2 da0 npdiag da1 ncs16 ndmack hirq iordy nhrd nhwr dmarq dd15 dd0 dd14 dd1 vdd dd13 dd2 gnd dd12 dd3 dd11 dd4 dd10 dd5 dd9 dd6 rd13 rd2 rd12 rd3 gnd rd11 rd4 rd10 rd5 rd9 rd6 rd8 cas rd7 cash/ nrweh nrwe ras gpio4/nccs2/ra8 ra7 ra0 ra6 ra1 ra5 ra2 ra4 ra3 dd8 rd15 rd0 rd14 rd1 dd7
preliminary/confidential subject to change without notice w88227f/W88227QD - 4 - 1999/10/1 rev: 0.70 1.3 pin arrangement number symbol type description remark 1 gnd p ground 2 dxi i decoder c rystal in connect to gnd if not used 3 dxo o decoder crystal out 4 alrck i/oz audio playback left/right clock 6ma, pu 5 abck oz audio playback bit clock 6ma, pu 6 asd nroe oz o audio playback serial data dram read enable, active low 6ma, pu 7 lrck i dsp left/right clock cmos level input 8 bck i dsp bit clock cmos level input 9 sdata i dsp serial data cmos level input 10 c2po sdata2 i i dsp c2 flag dsp serial data 2 cmos level input 11 scsd i subcode serial data 12 wfck i subcode write frame clo ck 13 scsyn i subcode sync 14 exck i/o subcode external clock 6ma, pu 15 nrsto o reset output, active low 6ma 16 gpio1 nfwe i/o o general purpose io flash write enable, active low 6ma, pu 17 gpio2 daout nfce i/o o o general purpose io digital audio output rom/flash chip enable, active low 6ma, pu 18 gpio3 nccs1 i/o o general purpose io configurable chip select, active low 6ma, pu 19 vdd p power 20 uxi i up crystal in 21 uxo o up crystal out 22 cko o clock output 6ma 23 npor i power on reset, acitve low pu 24 up10 i/o up port 1 4ma, pu 25 up11 i/o up port 1 4ma, pu 26 up12 i/o up port 1 4ma, pu 27 up13 i/o up port 1 4ma, pu 28 nhrst i host reset input, active low pu 29 up14 i/o up port 1 4ma, pu 30 up15 i/o up port 1 4ma, pu 31 up16 i/ o up port 1 4ma, pu 32 up17 i/o up port 1 4ma, pu 33 up30 i/o up port 3 (rxd) 4ma, pu
preliminary/confidential subject to change without notice w88227f/W88227QD - 5 - 1999/10/1 rev: 0.70 34 up31 i/o up port 3 (txd) 4ma, pu 35 up32 up33 i/o i/o up port 2 (int0) up port 3 (int1) 4ma, pu 36 up34 i/o up port 3 (t0) 4ma, pu 37 up35 i/o up port 3 (t1) 4 ma, pu 38 up36 i/o up port 3 (nwr) 4ma, pu 39 up37 i/o up port 3 (nrd) 4ma, pu 40 up00 i/o up port 0 8ma 41 up01 i/o up port 0 8ma 42 up02 i/o up port 0 8ma 43 up03 i/o up port 0 8ma 44 gnd p ground 45 up04 i/o up port 0 8ma 46 up05 i/o up port 0 8ma 47 up06 i/o up port 0 8ma 48 up07 i/o up port 0 8ma 49 psen i/o program store enable, acitve low 8ma, pu 50 a0 o external rom address 4ma 51 a1 o external rom address 4ma 52 a2 o external rom address 4ma 53 a3 o external rom address 4ma 54 a4 o external rom address 4ma 55 a5 o external rom address 4ma 56 a6 i/o external rom address 4ma, pu 57 a7 i/o external rom address 4ma, pu 58 up20 i/o up port 2 4ma, pu 59 up21 i/o up port 2 4ma, pu 60 up22 i/o up port 2 4ma, pu 61 up23 i/o up port 2 4ma, pu 62 up24 i/o up port 2 4ma, pu 63 up25 i/o up port 2 4ma, pu 64 up26 i/o up port 2 4ma, pu 65 gnd p ground 66 up27 i/o up port 2 4ma, pu 67 ndasp i/od drive active, active low 12ma, pu 68 ncs3 i host chip select 1, active low pu 69 ncs1 i host chip select 0, active low pu 70 da2 i host address 2 pu 71 da0 i host address 0 pu 72 npdiag i/od passed diagnostics, active low 12ma, pu 73 da1 i host address 1 pu 74 ncs16 od 16 - bit io select, active low 24ma
preliminary/confidential subject to change without notice w88227f/W88227QD - 6 - 1999/10/1 rev: 0.70 75 hirq oz host interrupt 12ma 76 ndmack i dma acknowledge, active low pu 77 iordy oz io channel ready 24ma 78 nhrd i host read strobe, active low pu 79 nhwr i host write strobe, active low pu 80 dmarq oz dam request 12ma 81 dd15 i/o host data 12ma, pu 82 dd0 i/o host data 12ma, p u 83 dd14 i/o host data 12ma, pu 84 dd1 i/o host data 12ma, pu 85 vdd p power 86 dd13 i/o host data 12ma, pu 87 dd2 i/o host data 12ma, pu 88 gnd p ground 89 dd12 i/o host data 12ma, pu 90 dd3 i/o host data 12ma, pu 91 dd11 i/o host data 12ma, p u 92 dd4 i/o host data 12ma, pu 93 dd10 i/o host data 12ma, pu 94 dd5 i/o host data 12ma, pu 95 dd9 i/o host data 12ma, pu 96 dd6 i/o host data 12ma, pu 97 dd8 i/o host data 12ma, pu 98 dd7 i/o host data 12ma, pu 99 rd15 i/o dram data 6ma, pu 100 rd0 i/o dram data 6ma, pu 101 rd14 i/o dram data 6ma, pu 102 rd1 i/o dram data 6ma, pu 103 rd13 i/o dram data 6ma, pu 104 rd2 i/o dram data 6ma, pu 105 rd12 i/o dram data 6ma, pu 106 rd3 i/o dram data 6ma, pu 107 gnd p ground 108 rd11 i/o dram dat a 6ma, pu 109 rd4 i/o dram data 6ma, pu 110 rd10 i/o dram data 6ma, pu 111 rd5 i/o dram data 6ma, pu 112 rd9 i/o dram data 6ma, pu 113 rd6 i/o dram data 6ma, pu 114 rd8 i/o dram data 6ma, pu 115 rd7 i/o dram data 6ma, pu 116 cas oz dram column addr ess strobe 8ma
preliminary/confidential subject to change without notice w88227f/W88227QD - 7 - 1999/10/1 rev: 0.70 117 cash nrweh oz oz dram column address strobe dram write enable, active low 8ma 118 nrwe oz dram write enable, active low 8ma 119 ras oz dram row address strobe 120 gpio4 nccs2 ra8 i/o o o general purpose io configurable chip select , active low dram address 6ma, pu 6ma 6ma 121 ra7 i/o dram address 6ma, pu 122 ra0 i/o dram address 6ma, pu 123 ra6 i/o dram address 6ma, pu 124 ra1 i/o dram address 6ma, pu 125 ra5 i/o dram address 6ma, pu 126 ra2 i/o dram address 6ma, pu 127 ra4 i /o dram address 6ma, pu 128 ra3 i/o dram address 6ma, pu
preliminary/confidential subject to change without notice w88227f/W88227QD - 8 - 1999/10/1 rev: 0.70 1.4 basic configuration dd15 - 0 da2 - 0 ndasp npdiag ncs3 ncs1 ncs16 hirq ndmack dmarq iordy nh rd nhwr up1 up0 a7 - 0 ide bus up3 up2 rom/ flash d7 - 0 a15 - 8 a7 - 0 gpio1/nfwe psen nwe noe gpio2/da0/nfce nhrst gpio3/nccs1 dram rd15 - 0 ra7 - 0 ras cash/nrweh cas nrwe dsp lrck dbck data c2po/data2 scsyn wfck scsd exck npor uxo uxi dxo dxi abck alrck asd nrsto crystal 33.8688 mhz nce nroe por logic gpio4/nccs2/ra8 cko
preliminary/confidential subject to change without notice w88227f/W88227QD - 9 - 1999/10/1 rev: 0.70 2. functional description 2.1 global function 2.1.1 decoder register access the decoder index register is latched from up port - 0 by the built - in 74373 at the f alling edge of internal ale signal. the high byte address of decoder register is defined by ccsa0 (40h) with default value 40h. : decoder register read (read ver) mov dptr,#0401ah movx a,@dptr : decoder register write (set ccsa1 as 0xc0h ) mov a,#0c0h mov dptr,#04041h movx @dptr,a 2.1.2 reset source the chip will be reset when master reset, including: (1) power on reset, (2) host reset or (3) reception of device reset command (opcode 08h) if arsten (2fh.w3) is high. the output of pin nrsto can be contr olled either by master reset or firmware. the state of pin nrsto is the inverse value of control bit rsto (43h.7) . & nrsto rsto (43h.7) nhrst npor + & device reset master reset ide i/f arsten(2fh.w3) & hardware reset
preliminary/confidential subject to change without notice w88227f/W88227QD - 10 - 1999/10/1 rev: 0.70 2.1.3 clock source and power management if the frequency on uxi is 33.8688 mhz, then the crystal on dxi can be saved. if the frequency on uxi is not 33.8688 mhz, then the input frequency on dxi must be 33.8688 mhz to support audio playback. a clock output pin cko can be used as clock source. if ckostp (43h.2) is set high, the output of pin cko holds a "high" status so t hat the external device is in idle mode. note that dxi should be connected to ground if not used. 1 0 playback logic up module programmable system clock ecc logic & dram i/f udma logic aclk=33.8688mhz dxi dxo uxi uxo dclks (43h.0) 1 0 uclks(8ah.3) 1 0 apins (90h.4) pskctl (59h) psken (1ah.w4) 1 0 aclks (43h.1) dclk sclk cko + ckostp (43h.2) decoder idle mode setting ckstp (19h.w7) stop the clock of decoder. the decoder exits idle mode on reset or host command. up8032 idle mode setting the idl (pcon.0) high stop the clock of up8032. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power - down mode when pd (pcon.1) is set high, t he chip enters the power - down mode. in this mode, the crystal feedback loop between uxi and uxo can be closed by setting pd (pcon.1) high, and that between dxi and dxo can be closed by setting xoff (8ah.7) high. in two - crystal case, xoff should be set b efore pd . these two loops resume on the following conditions. ea ehwk eiwk hiien arstien wake - up event x x x x x power on reset or host reset 1 1 x 1 x software reset by setting srst high 1 1 x x 1 device reset command 1 x 1 x x interrupt on int0 or i nt1 before entering power - down mode, internal pull - up resistors can be closed by setting puctl (98h).
preliminary/confidential subject to change without notice w88227f/W88227QD - 11 - 1999/10/1 rev: 0.70 2.1.4 multi - function pins the state of general - purpose i/o pins can be controlled through register gioctl (5fh) . 2.1.4.1 gpio1/nfwe configuration if the ide programm ing ready signature (e8) is high by executing the ide programming sequence, this pin is used as nfwe. otherwise, this pin is used as gpio1. 2.1.4.2 gpio2/daout/nfce configuration g2cf (5dh.3) daoen (87h.7) pin function remark 0b 0b nfce (default) 1b 0b gpio2 x 1b daout this pin is configured as nfce and output "low" after master reset. it holds "high" when up enter power - down mode by setting pd (pcon.1) high and returns to low active status when: 1. hardware reset, 2. software reset if hiien (2eh.w7) is set h igh, 3. or device reset command if arstien (2fh.w1) is set high. this function can be utilized to save power of external rom in sleep mode. if a pull - down resistor is connected to pin ra4, the pin is configured as gpio2 after master reset. if daoen (87h.7) is set high, this pin is used as daout, digital audio output. 2.1.4.3 gpio3/nccs1 configuration the value of ccsa1 (41h) is 00h after master reset. g3cf (5dh.2 - 0) function nccs1 active (low) condition remark 0xxb gpio3 n/a default 100b nccs1 (p2 = ccsa1) 101b nccs1 (p2 = ccsa1) & (p36 = "l") 110b nccs1 (p2 = ccsa1) & (p37 = "l") 111b nccs1 (p2 = ccsa1) & (p36 = "l" or p37 = "l")
preliminary/confidential subject to change without notice w88227f/W88227QD - 12 - 1999/10/1 rev: 0.70 2.1.4.4 gpio4/nccs2/ra8 configuration the value of ccsa2 (42h) is 00h after master reset. g4cf (5dh.7 - 4) function nccs2 active (low) condition remark 0xxxb ra8 output is tri - state after master reset and is enabled when rtc (2ah.2 - 0) 1 000b default 10xxb gpio4 n/a 1100b nccs2 (p2 = ccsa2) 1101b nccs2 (p2 = ccsa2) & (p36 = "l") 1110b nccs2 (p2 = ccsa2) & (p37 = "l") 1111b nccs2 (p2 = ccsa2) & (p36 = "l" or p37 = "l") 2.1.4.5 up32/up33 configuration up323s (43h.4) pin up32/up33 internal decoder interrupt remark 0b int0 int1 default 1b int1 int0 2.1.4.6 asd/nroe configuration this pin is used as nroe after master reset. it is configured as asd (audio playback serial data) when setting apout (90h.1 - 0) as 01b. 2.1.4.7 cash/nwreh configuration this pin is tri - state after master reset. it is configured as output when rtc (2ah,2 - 0) is 10xb. it is used as cash when twes (2ah,3) is low and as nrweh w hen twes (2ah,3) is high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 13 - 1999/10/1 rev: 0.70 2.1.5 ide programming mode this chip enters ide programming mode when the last initiation key is written to control port. the status can be verified by read ide programming ready signature (e8h) from feature port. 2.1.5.1 pin mapping flash pin name w88227 pin name function a15 - 8 up27 - up20 address high a7 - 0 a7 - 0 address low dq7 - 0 up07 - up00 data cen gpio2/daout/nfce chip enable oen psen output enable wen gpio1/nfwe write enable 2.1.5.2 ide programming sequence the following sequence is only an example. please properly adjust it to fit the specification of different flash. 1. select the drive 2. write initiation key to 1f3h/173h 3. read 1f3h/173h to verify ide programming ready signature (e8h) 4. write address to 1f4h/174h and 1f5h/175h 5. write data to 1f1h/ 171h 6. activates nfce by writing 04h to 1f2h/172h 7. activates nfwe by writing 05h to 1f2h/172h 8. releases nfwe by writing 04h to 1f2h/172h 9. go back to step 4 until all data are written 10. write address to 1f4h/174h and 1f5h/175h 11. activates nfoe by writing 06h to 1f2h /172h 12. read from 1f1h/171h to verify data 13. releases nfoe by writing 04h to 1f2h/172h 14. go back to step 10 until all data are verified 15. device reset (re - start up program counter from 0) or re - boot
preliminary/confidential subject to change without notice w88227f/W88227QD - 14 - 1999/10/1 rev: 0.70 2.1.5.3 initiation key the exact sequence for the initiation key in hex adecimal notation is: 4c, 26, 93, 49, a4, 52, a9, d4, 6a, b5, da, ed, f6, fb, 7d, be, df, 6f, 37, 1b, 0d, 86, c3, 61, b0, 58, 2c, 16, 8b, 45, a2, d1 2.1.5.4 ide programming registers port name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data 1f1h/171h r/ w flash data control 1f2h/172h w x x x x x fce foe fwe feature 1f3h/173h r/w programming signature address low 1f4h/174h w flash low address address high 1f5h/175h w flash high address
preliminary/confidential subject to change without notice w88227f/W88227QD - 15 - 1999/10/1 rev: 0.70 2.1.6 power - on setting pin ra7 - 0 are input with weak pull - up during mas ter reset or when rtc (2ah.2 - 0) is 000b. ra7 - 5 are used as power - on setting and ra4 - 0 can be used as general input when rtc (2ah.2 - 0) is 000b. the status of ra7 - 0 can be read from rasta (2dh,r) . pin ra7 4.7 k w pull - down operation mode remark no normal mo de default yes eup mode for ice debugging pin ra6 4.7 k w pull - down decoder chip select base address remark no 40xxh default yes c0xxh pin ra5 4.7 k w pull - down operation mode remark no normal mode default yes up test mode for factory test only
preliminary/confidential subject to change without notice w88227f/W88227QD - 16 - 1999/10/1 rev: 0.70 2.1.7 external up (eup) mode if a 4.7k pull - down is connected to pin ra7 during power - on, this chip enters the external up (eup) mode. in eup mode, the internal up do not work and some pins are redefined by the following table to work with an external up. this t esting mode is specially designed for firmware debug using ice. note that one ttl is needed to support external up reset signal in eup mode. normal i/o eup mode i/o remark p0 i/o ud i/o p1 i/o n/a z p2 i/o n/a i be used to generate internal ucsb a7 - 0 o a7 - 0 o up30 i/o n/a z up31 i/o n/a z up33/up32 i/o uintb o one 0 ohm option resistor may be needed up34 i/o n/a z up35 i/o n/a z up36 i/o uwrb i up37 i/o urdb i psen o alein i one 0 ohm option resistor may be needed 2.1.8 up test (upt) mode if a 4.7k pull - down is connected to pin ra5 during power - on, this chip enters the up test (upt) mode. in upt mode, some pins are redefined by the following. this mode is for factory test only. normal i/o upt mode i/o remark p32/p33 i/o p32 i/o a7 o p3 3 i/o a6 o ale o
preliminary/confidential subject to change without notice w88227f/W88227QD - 17 - 1999/10/1 rev: 0.70 2.2 decoder function 2.2.1 dram interface 2.2.1.1 memory layout the whole dram can be divided into sector data area and working area . sectors from dsp are buffered into sector data area and then are retrieved for ecc/edc operation. some information is stored in working area for transfer to host on request, for example, toc. sector data buffering is a block - based ring operation. if the decoded - block - number in ddbh/l (29h/28h) is n - 1 , the sector is buffered into block with number n . the decoded - blo ck - number is automatically incremented by one at each sync. when the decoded - block - number equals the value in wbrch/l (57h/56h) , the sector is buffered into the block with number specified by wbrbh/l (55h/54h) . the data transfer is also a block - based ring operation if multi - block - transfer is used. the transfer ring is controlled by dtrch/l (53h/52h) and dtrbh/l (51h/50h) . the buffer ring and transfer ring are usually defined in the same range. ring ceiling ring base working area sector data area block number wrap around block size is a00h if rlc=3 or c00h if rlc=2 ring ceiling = 2fh ring base = 00h block #2fh block #00h block #2dh block #01h 1ffffh 1e000h 1d600h 00000h 00a00h 01400h example: 128k x 8, rlc[1:0](2bh.1-0) = 3 illustration diagram for memory layout
preliminary/confidential subject to change without notice w88227f/W88227QD - 18 - 1999/10/1 rev: 0.70 2.2.1.2 block configuration the configuration of each memory block depends on the data format. the following tables show the recommended configuration of block whose size is a00h and c00h, respectfully. if bia (09h/08h) = 000ch and rlc (2bh.1 - 0) = 3, block size is a00h. item mode 1 mode 2 mode2 form1 mode2 form2 cd - da sync 000h (12) 000h (12) 000h (12) 000h (12) n/a header 00ch (4) 00ch (4) 00ch (4) 00ch (4) n/a subheader n/a n/a 010h (8) 010h (8) n/a user data 010h (2048) 010h (2336) 018h (2048) 018h (2324) 000h (2352) ecc & edc 810h (288) n/a 818h (280) 92ch (4) n/a subcode 980h (96) 980h (96) 980h (96) 980h (96) 980h (96) q - channel 9e0h (12) 9e0h (12) 9e0h (12) 9e0h (12) 9e0h (12) note : table format: starting offset address (no. of bytes) if bia (09h/08h) = 000ch and rlc (2bh.1 - 0) = 2, block size is c00 h. item mode 1 mode 2 mode2 form1 mode2 form2 cd - da sync 000h (12) 000h (12) 000h (12) 000h (12) n/a header 00ch (4) 00ch (4) 00ch (4) 00ch (4) n/a subheader n/a n/a 010h (8) 010h (8) n/a user data 010h (2048) 010h (2336) 018h (2048) 018h (2324) 000h ( 2352) ecc & edc 810h (288) n/a 818h (280) 92ch (4) n/a c2 flag a00h (294) a00h (294) a00h (294) a00h (294) a00h (294) subcode b80h (96) b80h (96) b80h (96) b80h (96) b80h (96) q - channel be0h (12) be0h (12) be0h (12) be0h (12) be0h (12)
preliminary/confidential subject to change without notice w88227f/W88227QD - 19 - 1999/10/1 rev: 0.70 the rule for c onfiguration is that the first byte of the sector is stored at: biah/l(09h/08h,w) - 0ch and the following byte is stored into the incremented offset address. if the offset address reaches the block limit, the next offset address is wrap around to zero. for example, the byte following that at offset 9ffh is at 000h if block limit is a00h. by this mechanism and following example settings, the first byte of user data is always located at 000h. the subcode (980h/b80h) and q - channel (9e0h/be0h) data are stor ed at fixed address if its associated function is enabled. but the 2352 bytes sector data (including sync, header, user data, ecc, edc for mode 1 sector) can be re - arranged to any other area in the block. 2.2.1.3 linear transfer address counter when latxf (03h.w7 ) is high, the address defined by racu/h/l (2dh/1dh/1ch,w) is loaded to a internal linear transfer address counter at the begin of data transfer. this separate counter leaves racu/h/l (2dh/1dh/1ch,w) free for up to dram access after the transfer is trigge red. the up can access dram data defined by racu/h/l (2dh/1dh/1ch,w) regardless the setting of latxf (03h.w7) .
preliminary/confidential subject to change without notice w88227f/W88227QD - 20 - 1999/10/1 rev: 0.70 2.2.1.4 linear address v.s. block - offset address the microprocessor can write/read external ram through register rawr/ramrd (1eh) based on linear addr ess defined by racu/h/l (2dh/1dh/1ch,w) . but the operation of data transfer from dram to host can base on block - offset address or linear address. the following equation defines the relation between these two types of address. linear address = (block num ber block size) + address offset data transfer in working area conditions: 64 bytes of toc data are stored starting from linear address 3ea00h at disc initialization and toc is requested by host (block size is a00h). a) sequence at disc initi alization: a) set racl (1ch) as 00h b) set rach (1dh) as eah c) set racu (2dh) as 03h d) wait utby (1fh.7) low e) write data to register ramwr (1eh) f) goto step e) until all 64 bytes are written to dram b1) setting for block - offset address transfer : - set tbh/l (25h/24h) as 0064h - set tach/l (05h/04h) as 0200h - set twch/l (03h/02h) as 001fh b2) setting for linear address transfer: - set racl (1ch) as 00h - set rach (1dh) as eah - set racu (2dh) as 03h - set twch/l (03h/02h) as 801fh data transfer in user area case 1: the 2048 bytes of user data are requested by host. set tbh/l (25h/24h) as 001fh set twch/l (03h/02h) as 03ffh set tach/l (05h/04h) as 0010h case 2: the 288 bytes of edc&ecc data are request by host. set tbh/l (25h/24h ) as 001fh set twch/l (03h/02h) as 008fh set tach/l (05h/04h) as 0810h if the requested data is not stored continuously in dram, e.g., header and edc&ecc data, more than one transfer has to be triggered.
preliminary/confidential subject to change without notice w88227f/W88227QD - 21 - 1999/10/1 rev: 0.70 2.2.2 microcontroller interface 2.2.2.1 programmable system clock the internal system frequency is controlled by cctl1 (1ah,w) and pskctl (59h,w) . register pskctl (59h,w) should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. if both psken (1ah.w4) and psksel (59h.w7) are high, psk 5 - 0 (59h.5 - 0) are used to controlled the internal system frequency. register pskctl (59h,w) should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. the equation is: frequency of system clock = frequency of aclk ( psk[ 5:0] + 2) ? 16 the variation of the resultant system frequency is normally less than 5%. if the frequency of aclk is 33.8688 mhz, psken (1ah.w4) and psksel (59h.w7) are high: psk5 - 0 system frequency remark 0fh 36 mhz 11h 40.2 mhz 13h 44.4 m hz 15h 48.7 mhz 17h 53 mhz 19h 57.2 mhz 1bh 61.4 mhz
preliminary/confidential subject to change without notice w88227f/W88227QD - 22 - 1999/10/1 rev: 0.70 2.2.3 host interface the host interface is a standard atapi interface with enhanced ultra dma support. the ultra dma protocol could double the current burst transfer rate of 16.6mb/sec to 66mb/sec without hardware changes such as termination devices or different cabling. 2.2.3.1 ultra dma mode setting this decoder is capable of supporting ultra dma mode 4. device firmware could claim that ultra dma mode 4 and below are supported in identify device inform ation. the value of udt1 - 0 (8ah,5 - 4) defines the ultra dma timing factor, udtf , which control the timing of ultra dma transfer. tcyc = ( 2 + udtf ) tudma where tudma is clock period depends on setting of udta (8ah.6) and uclks (8ah.3) and tcyc is ultr a dma cycle time (from dstrobe edge to dstrobe edge) device firmware should set udtf according to the clock source and the assigned ultra dma transfer mode after host issues set feature command. if there are frequent crc errors in data - in bursts, device firmware may switch system to slower ultra dma mode by increasing udtf to improve data integrity. example : if uclks (8ah.3) is high and frequency of aclk is 33.8688mhz, the udtf should be the following value to abide by the determined ultra dma mode. ultra dma t2cyc min. spec. t2cyc udta udtf mode 0 230 ns 236 ns 0 2 mode 1 154 ns 177 ns 0 1 mode 2 115 ns 118 ns 0 0 mode 3 86 ns 88.6 ns 1 1 mode 4 57 ns 60 ns 1 0 2.2.3.2 ultra dma error handling flag ucrcokb (30h.r3) is used to determine if a crc error event has occurred during latest ultra dma burst. if aucrcen (18h.2) and ascen (18h.5) are both set high, the automatic status complete logic would not be triggered if ucrcokb (30h.r3) is high. therefore, firmware should check ucrcokb (30h.r3) flag after each ultra dma burst. if a crc error has occurred, firmware should set chk (37h.0) to one and manually trigger status complete.
preliminary/confidential subject to change without notice w88227f/W88227QD - 23 - 1999/10/1 rev: 0.70 2.2.3.3 ultra dma data - out the programming of ultra dma transfer is similar to that of multi - word dma transfer. one thing should be note d is that device should prepare to receive one additional word at the end of a data out burst . since 12 - byte packet fifos are used to receive data in ultra dma data - out transfer, the value of registers twch/l (03h/02h) should be set 4 instead of 5. then firmware should repeatedly read register pfar (00h,r) after transfer end interrupt asserts until flag pfneb (01h.r7) becomes one. data - out transfer sequence: 1. tenden (01h.w6) ? 1 2. asctrl (18h,w) ? 58h 3. hictl0 (1fh.w) ? 0bh // udma data - out 4. twc (0 3h/02h,w) ? min(0004h, byte_cnt/2 - 1) 5. adtt (17h.w2) ? 1 // automatic data transfer trigger 6. wait tendb (01h.r6) = 0 and tdir (30h.r5) = 1 and fpkt (30h.r1) = 1 7. tack (07h,w) ? ffh 8. read pfar (00h,r); byte_cnt =byte_cnt - 1 9. if pfneb (01h.r7) is low, repeat step (8) 10. if (byte_cnt 1 0) goto step (4) 11. sct (17h.0) ? 1 // status complete trigger
preliminary/confidential subject to change without notice w88227f/W88227QD - 24 - 1999/10/1 rev: 0.70 2.2.3.4 bsy flag control bsy is bit - 7 of atapi status register. bsy set bsy clear chip reset set clrbsy (20h.w4) if apkt (30h.r0) is low host reset set drqt (17h.w1) if pio (1fh.2 ) is high set bit srst in atapt device control register host issue atapi command (opcode a0h) if apkten (18h.7) is high set setbsy (20h.w3) if apkt (30h.r0) is low automatic status completion sequence, enabled by sct (17h.w0) or ascen (18h.5) host issues execute diagnostics command (opcode 90h) dfrdyb (01h.r1) becomes low after adtt (17h.w2) is set, if pio (1fh.2 ) is high host issue ata command when drive is selected transfer end if adcen (18h.6) is enabled set adtt (17h.w2) set dsct (17h.w5 ) if abyen (18h.1) is enabled - lasting 3 system clocks 2.2.3.5 pin hirq control pin hirq is set or clear by the following conditions if the drive is selected and nien is enabled in the atapi device control register. hirq is activated by the following events : automatic packet transfer sequence, enabled by apkten (18h.7) automatic status completion sequence, enabled by sct (17h.w0) or ascen (18h.5) write misc0 (2eh) with bit - 3 high hirq is de - activated by the following events: chip reset or host reset or firmw are rest set bit srst in the atapi device control register high host issue ata command while the drive is selected host read atapi status register while the drive is selected write misc0 (2eh) with bit - 3 low
preliminary/confidential subject to change without notice w88227f/W88227QD - 25 - 1999/10/1 rev: 0.70 2.2.4 decoder logic 2.2.4.1 sync detection/insertion the syn c field of cd - rom data is recorded as following: 1 (00h) bytes, 10 (ffh) bytes and 1 (00h) byte. this sync field is detected for sector synchronization if sden (0bh.w6) is enabled. to prevent loss of synchronization caused by broken sync, an internal cou nter can provide inserted sync signal if sien (0bh.7) is enabled. there are no sync bytes in cd - da format, so sden (0bh.w6) should not be set. 2.2.4.2 descramble bytes 12 to 2351 of each cd - rom sector is scrambled in decoding. setting dscren (0bh.5) high enables the descramble logic. descramble logic should be disabled while reading of cd - da data. 2.2.4.3 disk - monitor mode the decoder logic is in disk - monitor mode if ctrl0 (0ah,w) is set as 80h. in disc - monitor mode, no ecc correction and edc checking is carried. the sector ready interrupt flag srib (01h.r5) is immediately generated when the header bytes are available in head0 - 3 (04h - 07h,r) . the header bytes in disc - monitor mode are less trustworthy than that in buffer - correction mode. 2.2.4.4 parallel ecc correction the err or correction of the cd - rom sector is carried by a reed - solomon product - like code (rspc). the rspc is a product code over gf(2 8 ) field which is generated by the primitive polynomial p(x) = x 8 + x 4 + x 3 + x 2 + 1 the primitive element a of gf(2 8 ) is a = ( 00000010) where the right - most bit is the least significant bit. the data is divided into high byte plane and low byte plane before decoding. the rspc decoding, operating on bytes, is then applied twice, once to the high byte plane, once to the low byte p lane. to improve the efficiency of rspc decoding, a parallel ecc correction logic is implemented on chip. after sync detection and descramble, the parallel ecc correction is carried on high byte plane and low byte plane simultaneously. this correction s cheme is about 33% faster than conventional decoder. the q - code correction and p - code correction are enabled by qcen (0ah.w1) and pcen (0ah.w0) respectively. if both correction operations are enabled, q - code correction is executed first. the corrected da ta are written back to external ram if cwen (0bh.w4) is high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 26 - 1999/10/1 rev: 0.70 2.2.4.5 edc checking the edc checking logic carry 32 - bit crc checking on error corrected data according to its mode. the checking result can be monitored through flag crcok (0ch.r7) . if the result is error, the errors in sector may exceed the capacity of correction logic and some data might be miscorrected. 2.2.4.6 real time edc checking if real time edc checking logic is enabled by setting rtedc (0ah.w6) high, the remainder of serial data is calculated whil e the sector is being buffered into dram. the sector ready interrupt flag srib (01h.r5) is immediately activated at next sync if the resultant remainder is zero, i.e., no edc error. if there is error, the specified error correction is then applied to the buffered data. this function should not be enabled in disk - monitor mode. 2.2.4.7 disc format selection before enable decoder logic through register ctrl0 (0ah,w) , appropriate value should be set to register ctrl1 (0bh.w) according to different disc format. if acen (0ah.w4) and m2rq (0bh.w3) are both high, the type of error correction is automatically determined by form bit in the subheader byte rather than setting of f2rq (0bh.w2) . the value of acen (0ah.w4) does not affect the yellow - book mode - 1 correction. disc format sien (0bh.7) sden (0bh.6) descren (0bh.5) cwen (0bh.4) m2rq (0bh.3) f2rq (0bh.2) cd - da 1 0 0 0 0 0 yellow book mode 1 1 1 1 1 0 0 yellow book mode 2 1 1 1 0 0 0 cd - rom xa m2f1 1 1 1 1 1 0 cd - rom xa m2f2 1 1 1 x 1 1 2.2.4.8 dsp main data format i f d2en (1bh.w3) is set high, pin c2po/sdata2 is used as second serial data input pin. the two - bit format can dramatically reduce the frequency on dsp main data interface and improve emi. dspsl dsp data format 07h toshiba 0bh winbond two - bit 24h sanyo a3h sony 48 - bit slot c3h philip
preliminary/confidential subject to change without notice w88227f/W88227QD - 27 - 1999/10/1 rev: 0.70 2.2.4.9 cd - da data & q - channel extraction there are no sync bytes in cd - da format, so absolute msf bytes of mode 1data - q (adr = 0001) should be utilized as synchronization when reading cd - da data. q - channel extraction can be enabled by setting both qen (80h.w5) and scen (2ch.w6) high. once decoder and q - channel extraction are both enabled, the extracted q - channel bytes are written into the dram starting from offset 9e0h of each block regardless of what mode of data is set. the first byte of q - channel (control and adr) can be retrieved from offset 9e0h. when qsigen (21h.4) is set high, a signature 0xffh will be placed in offset 9e0h if crc checking of q - code is erroneous. the absolute msf information can be retrieved from of fset 9e7h, 9e8h and 9e9h of each block. there is an alternative way to access msf of q - channel information. if control bit qmsf (80h.w4) is set high, the corresponding msf bytes in q - channel information would be automatically loaded into head0 - 2 (04h - 06h, r) when each byte is ready from dsp. the register head3 (07h,r) hold first byte of data - q, (control and adr) or 0xffh if crc checking of q - channel is erroneous. if q - channel extraction is enabled, device firmware can check flag qcrcok (22h.r4) to see if t here is a crc error in the latest q - channel information. smd1 format setting: biah/l (09h/08h) = 000ch ctrlw (10h.w) = 30h sictl0 (21h) = 30h sictl1 (2ch,w) = 55h (smd1 mode) qen (80h.w5) = 1 and qmsf (80h.w4) = 1 sdbs (88h.w4) = 1 and sbck (88h .w3) = 1 ctrl1 (0bh.w) = 80h ctrl0 (0ah.w) = 84h scib (01h.r0) substa (22h.r) following the above setting, there is no need to set sictl (21h.w), scbh/l (27h/26h,w) and sctc (5ah,w). in order to transfer the whole sector to host, 2352 bytes, the value in t wch/l (03h/02h) should be 0497h and the value in tach/l (05h/04h) should be 0000h.
preliminary/confidential subject to change without notice w88227f/W88227QD - 28 - 1999/10/1 rev: 0.70 2.2.4.10 target search the target search logic is initialized by: (1) setting search limit, (2) setting target and (3) setting targen (80h.w7) high. after the decoding is triggere d through ctrl0 (0ah,w), the first sector ready interrupt is generated when: i) the target sector is found, ii) header is larger than target or iii) search limit is reached. if event ii) or iii) occurs, the microprocessor may read out head0 - 2 (04h - 06,r) t o determine the current distance from target. setting lttien (80h.w2) and tnfen (80h.w1) high can generate the associated interrupt flag on srib (01h.r5) before the target is found. 2.2.4.11 automatic header comparison the automatic header comparison logic is ena bled by setting targen (80h.w7) and hceen (80h.w0) high. after the first target is found, the value in target (84h - 86h) increases from (t - 1) to t . and the decoder is changed from disk - monitor mode to buffer - correction mode. then head0 - 2 (04h - 06h,r) ar e compare with target (84h - 86h) and generate flag hcei (80h.r0) at the end of edc - checking. unless flag staerr (80h.r6) or hcei (80h.r0) is generated, the value in target (84h - 86h) is automatically incremented by one and ready to be compared with next sec tor. 2.2.4.12 status collection the status collection logic is enabled if any bit in the status - mask - register (8ch - 8fh,w) is set high. at the end of edc - checking, flag staerr (80h.r6) becomes high if any status bit error that is enabled by its associating mask b it occurs. the microprocessor can reduce the system overhead by checking staerr (80h.r6) rather than reading out stat (0ch - 0fh,r) . 2.2.4.13 buffer - independent - correction buffer - independent - correction (bic) is enabled if bicen (9ah.7) is high. in bic mode, the cor rection is triggered when the sectors not decoded in buffer is larger than one. in bic mode, the ddbh/l (29h/28h) controls the decoding block and increments at the end of edc - checking, except erroneous sectors. meanwhile, the buffering block (internal) i ncrements at each sync. because of the independence of the buffering block and decoding block, the automatic repeat correction can be enabled by setting rclim3 - 0 (9ch.3 - 0) the maximum rounds of repeat correction. 2.2.4.14 remove frequent srib & automatic cache m anagement control bit rmsri (5ch.0) should be set when entering buffer mode and be disabled in decoder_off routine. when rmsri (5ch.0) is high, flag srib (01h.r5) is generated only by staerr (80h.r6) , lastbk (80h.r3) or hcei (80h.r0) . so after the targe t is found and buffer - correction mode is enabled, the first interrupt is generated by lastbk (80h.r3) if there is no decoding error. setting rmsri (5ch.0) high can reduce the overhead of microcontroller while the automatic cache management is used.
preliminary/confidential subject to change without notice w88227f/W88227QD - 29 - 1999/10/1 rev: 0.70 sinc e the srib (01h.r5) interrupt is removed except for erroneous sectors, the cache management should be implemented through tcc (9dh) . if tcincen (9ch.5) is high, tcc (9dh) increments at the end of edc - checking if there is no staerr (80h.r6) or hcei (80h.r0 ) error. if acmen (9ch.6) is high, tcc (9dh) decrements at the end of each data - in block transfer. the transfer of working area data should be implemented as linear transfer to prevent error. writing value to skipc (9eh) can be used to implement the cache - partial - hit event. for the cache - miss event, tcc (9dh) should be set 0. the stop of dsp buffering is implemented by following setting ininitialization to prevent buffer wrap - around: bicctl (9ah) ? b0h buflim (9bh) ? cache_limit the following figure show s an example flowchart under following conditions: buffer - independent - correction is enabled remove frequent srib is enabled in buffer mode automatic transfer and cache management is enabled linear address transfer for working area data is enabled in this c ase, the flag tendb (01h.r6) is generated only when the last block is transferred to host, i.e., ttc (9fh) is zero.
preliminary/confidential subject to change without notice w88227f/W88227QD - 30 - 1999/10/1 rev: 0.70 set tsl(83h) ymonitor_mode = 1 ydec_idle = 0 ctrlw(10h) = 50h bicctl(9ah) = b0h acctl(9ch) = 111xxxxxb tcc(9dh) = 00h set ttc(9fh) read_command cache_check cahce_hit? ydec_idle? set skipc(9eh) no decoder_stop no yes n - 1 = ring_size return yes decoder_restart decoder_restart return decoder_on target(84h-86h) = t - 1 tarctl(80h) = 10xx1111b set bia(09h/08h) ctrl1(0bh) = f0h for mode 1 = f8h for mode 2 ctrl0(0ah) = a7h return yes srib(01h.r5) ymonitor_mode? t - 1 = target(84h-86h) - 1 decoder_stop return ymonitor_mode? ctrl0(0ah) = 80h no tnfi(80h.1) or ltti(80h.2) yes ymonitor_mode = 0 no decoder_on return yes mask(8ch) = 80h decoder_stop ctrlw(10h) = 10h return ctrl0(0ah) = 00h n - 1 = ddb(29h/28h) enctl2(5ch) = 09h return ddb(29h/28h) = n - 1 enctl2(5ch) = 08h no ydec_idle = 1 decoder_on power_on others return decoder_ini return decoder_ini tbh/l(25h/24h) = 00h set hictl(1fh) asctrl(18h) = 74h set twch/l(03h/02h) set tach/l(05h/04h) buflim(9bh) = buf_lim
preliminary/confidential subject to change without notice w88227f/W88227QD - 31 - 1999/10/1 rev: 0.70 2.2.5 audio - playback 2.2.5.1 configuration phase 1. configure input/output pin for audio - playback through apcnf (90h). - bit 6 : audio playback interrupt enable - bit 4: audio reference clock select - bit 3,2: audio input reference clock setting - bit 1:0: audio data output setting 2. select audio - playback output format through apfmt (91h). after configuration, pin abck becomes a ctive but data pin keep "mute." 2.2.5.2 playback phase if the desired data sectors are buffered in dram, the following steps can trigger audio playback: 1. set audio - playback start block through apbkh/l (93h/92h). 2. enable audio - playback by setting apen (90h.7) high. 3. w ait for interrupt or polling flag apib (01h.r2). 4. if apien (90h.6) is enabled, write apack (97h,w) to deactivate audio - playback - interrupt. 5. if buffer is not empty or end of command, go to step 3. 6. disable audio - playback by setting apen (90h.7) low. the status of playback is directly controlled by the setting of apen (90h.7). so the buffer should be carefully managed to prevent noise or broken song. 2.2.5.3 iec - 958 digital audio output the digital output function complies with the iec - 958 standard. this internal func tion is automatically enabled after configuration of audio playback function. the digital audio signal is output to pin gpio2/daoout/nfce when daoen (87h.7) is set high after master reset.
preliminary/confidential subject to change without notice w88227f/W88227QD - 32 - 1999/10/1 rev: 0.70 2.2.6 function differences between w88227 and w88113cf w88227 w88113c f internal linear address transfer counter is added rac(1ch,1dh,2dh) can not be accessed during linear address transfer target (84h - 86h) decrement by setting tardec (16h.w0) high target decrement must be performed by up host write to packet fifo generat e automatic status completion only if ascen (18h.w5) is high and pffacb (01h.w3) is low host write to packet fifo generate automatic status completion if ascen (18h.w5) is high tcc (9dh) update source is controlled by tccctl (58h.3 - 0) n/a also support 2 nrwe dram support 2 cas dram only ctrl0 can read from 0ah ctrl0 is write only to 0ah ctrl1 can read from 0bh ctrl1 is write only to 0bh tarctl can read from 10h tarctl is write only to 80h intctl can read from 11h intctl is write only to 01h sictl0 c and read from 21h sictl1 is write only to 21h memcf can read from 2bh memcf is write only to 2bh sictl1 can read from 2ch sictl1 is write only to 2ch new control bit pffacb (01h.w3) n/a new control bit tardec (16h.w0) n/a new control bit tarinc (16h.w 1) n/a new control bit tarinc7 (16h.w2) n/a new control bit d2en (1ah.w3) n/a new control bit ascend (21h.6) n/a new control bit qsigen (21h.5) n/a new control bit twes (2bh.3) n/a new register rasta (2dh,r) n/a control bits (2fh.w3 - 2) are re - define d control bits (2fh.w3 - 2) as arsts new global control registers (40h - 43h) n/a new register tccctl (58h) n/a new control bit dspdw (5bh.2) n/a new control bit udta (8ah.6) n/a new control bit apacenb (93h.5) n/a hrsts (2fh.w5 - 4) are obsolete available alrt (5bh.3) is obsolete available asrit (5bh.6) is obsolete available ale2 (5ch.3) is obsolete available lsta (48h - 4bh), lhd (4ch - 4fh) are obsolete available
preliminary/confidential subject to change without notice w88227f/W88227QD - 33 - 1999/10/1 rev: 0.70 2.2.7 decoder register map index type name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - r/w ir ind ex 00h r pfar b7 b6 b5 b4 b3 b2 b1 b0 01h 11h w r intctl pfneen tenden srien 0 pffscb 0 dten 0 01h r intrea pfne tend srib hcib tbsyb apib dfrdyb scib 02h r/w twcl b7 b6 b5 b4 b3 b2 b1 b0 03h r/w twch latxf x x x b11 b10 b9 b8 04h w tacl a7 a6 a5 a4 a3 a2 a1 a0 05h w tach a15 a14 a13 a12 a11 a10 a9 a8 06h w thtrg data unused 07h w tack data unused 04h r head0 header minutes (bcd) 05h r head1 header second (bcd) 06h r head2 header frames (bcd) 07h r head3 header mode (bcd) 08h w bial a7 a6 a5 a 4 a3 a2 a1 a0 09h w biah a15 a14 a13 a12 a11 a10 a9 a8 0ah r/w ctrl0 decen rtedc edcen acen x bufen qcen pcen 0bh r/w ctrl1 sien sden dscren cwen m2rq f2rq mcrq shden 0ch r stat0 crcok ilsyn nosyn lbkf wshort sbkf 0 uceblk 0dh r stat1 bi2 bi1 bi0 hder a 0 0 0 shdera 0eh w dhtack data unused 0eh r stat2 rmod3 rmod2 rmod1 rmod0 mode2 nocor rfera rform 0fh w frst data unused 0fh r stat3 stavab 0 ecf 0 0 0 c2df 0 10h w ctrlw 0 swen sdss dcken 0 c2wen eccrst dsprst 11h w crtrg data unused crrl 12h r/w mbtc0 mbvab/r mbinc/r 0 mbc4 mbc3 mbc2 mbc1 mbc0 13h r/w mbtc1 0 0 0 0 0 mbtien mbtfen incmbc 14h w ectrl 0 0 0 0 0 0 ir7f disai 14h r subho subheader(file) 15h r subh1 subheader(channel) 16h r subh2 subheader(submode) 17h r subh3 subheader(coding) 16h w evtrg x x x x x tarinc7 tarinc tardec 17h w astrg 0 csrt dsct sigt cpft adtt drqt sct 18h r/w asctrl apkten adcen ascen autoen stwcen aucrcen abyen pktien 19h w cctl0 ckstp x jpss 0 csk3 csk2 cks1 csk0 1ah w cctl1 clkoen tsync xininv psken clk1 clk0 0 xtald2 1ah r ver e7h 1bh w dspsl c2ml s16o lchp sft8 d2en sel16 dir edge 1bh r c2beb b7 b6 b5 b4 b3 b2 b1 b0
preliminary/confidential subject to change without notice w88227f/W88227QD - 34 - 1999/10/1 rev: 0.70 1ch w racl a7 a6 a5 a4 a3 a2 a1 a0 1dh w rach a15 a14 a13 a12 a11 a10 a9 a8 2dh w racu 0 0 0 0 a19 a18 a17 a16 1eh w ramwr b7 b6 b5 b 4 b3 b2 b1 b0 1eh r ramrd b7 b6 b5 b4 b3 b2 b1 b0 1fh w hictl0 x x x laen mdma pio dinb udma 1fh r stat5 utby 0 0 0 mdma pio dinb udma 20h r/w hictl1 0 pdiagen daspen clrbsy setbsy scod rdyen io16en 21h w sictl0 0 0 ascend qsigen pqenb subcs2 subcs1 s ubcs0 22h w sciack data unused 22h r substa x x x qcrcok x mss nesbk iss 24h r/w tbl b7 b6 b5 b4 b3 b2 b1 b0 25h r/w tbh data unused b8 26h r/w scbl b7 b6 b5 b4 b3 b2 b1 b0 27h r/w scbh data unused b8 28h r/w ddbl b7 b6 b5 b4 b3 b2 b1 b0 29h r/w dd bh data unused b0 2ah w ramcf rftyp rftrg x swap b3 rtc2 rtc1 rtc0 2ah r ramcf rftyp rftrg rfc swap twes rtc2 rtc1 rtc0 2bh r/w memcf 0 0 0 0 dfrst frdy rlc1 rlc0 2ch r/w sictl1 sbxck scen cd2sc scien exinv exop scf1 scf0 2dh r rasta rasta7 rasta6 ras ta5 rasta4 rasta3 rasta2 rasta1 rasta0 2eh w misc0 hiien 0 drveb mdrv hirq shien 0 0 2eh r miss0 1 1 srub mdrvf hintf 1 npdiag ndasp 2fh w misc1 arrc sarrc hrsts1 hrsts0 arsts1 arsts0 arstien arwc 2fh r miss1 srst atac diag shdc arst rst frst hrst 30h w arstack data unused 30h r miss2 srstd cmdc tdir mbti ucrcokb crst fpkt apkt 31h w aterr b7 b6 b5 b4 mcr abrt eom ili 31h r atfea 0 0 0 0 0 0 0 dma 32h r/w atint 0 0 0 0 0 0 io cod 33h r/w atspa b7 b6 b5 b4 b3 b2 b1 b0 34h r/w atblo b7 b6 b5 b4 b3 b2 b1 b0 35h r/w atbhi b7 b6 b5 b4 b3 b2 b1 b0 36h r/w atdrs 1 l 1 drv 0 0 0 0 37h w atsta 0 drdy 0 dsc drq corr 0 check 37h r atcmd b7 b6 b5 b4 b3 b2 b1 b0 38h w aserr 0 0 0 0 0 0 0 scheck 38h r atsta bsy drdy b5 dsc drq corr 0 check 39h w aserr 0 0 0 0 0 sabrt 0 0 39h r aterr b7 b6 b5 b4 mcr abrt eom ili 3ah r lddbl latched ddbl 3bh r lddbh latched ddbh 3dh w apksta 0 0 0 adsc 0 0 0 0 3eh w ascsta 0 adrdy 0 0 0 acorr 0 acheck
preliminary/confidential subject to change without notice w88227f/W88227QD - 35 - 1999/10/1 rev: 0.70 3fh r/w shdctl 0 shdrv shdrvl 0 0 dasps2 dasps1 daspss 40h r/w ccs a0 b7 b6 b5 b4 b3 b2 b1 b0 41h r/w ccsa1 b7 b6 b5 b4 b3 b2 b1 b0 42h r/w ccsa2 b7 b6 b5 b4 b3 b2 b1 b0 43h r/w glctl1 rsto x x up323s x ckostp aclks dclks 50h r/w dtrbl b7 b6 b5 b4 b3 b2 b1 b0 51h r/w dtrbh data unused b8 52h r/w dtrcl b7 b6 b5 b4 b3 b2 b1 b0 53h r/w dtrch data unused b8 54h r/w wbrbl b7 b6 b5 b4 b3 b2 b1 b0 55h r/w wbrbh data unused b8 56h r/w wbrcl b7 b6 b5 b4 b3 b2 b1 b0 57h r/w wbrch data unused b8 58h r/w tccctl x x x x tccctl3 tccctl2 tccctl1 tccctl0 59h r psksta locked o nlock psk5 psk4 psk3 psk2 psk1 psk0 59h w pskctl psksel locksel psk5 psk4 psk3 psk2 psk1 psk0 5ah w sctc d7 d6 d5 d4 d3 d2 d1 d0 5bh r/w enctl1 asdma obsolete dsp1stb b4 alectl dspdw dra b0 5ch r/w enctl2 x x x x obsolete syncp b1 rmsri 5dh r/w giocf g4cf3 g4cf2 g4cf1 g4cf0 g2cf g3cf2 g3cf1 g3cf0 5eh r/w pskcnt x x x pskcnt4 pskcnt3 pskcnt2 pskcnt1 pskcnt0 5fh r/w gioctl g4oen g3oen g2oen g1oen gio4 gio3 gio2 gio1 80h 10h w r tarctl targen dscen qen qmsf astopb ltten tnfen hceen 80h r tarsta targ ed staerr bin0 dsfuli lastbk ltti tnfi hcei 81h w dstl b7 b6 b5 b4 b3 b2 b1 b0 81h r dscl b7 b6 b5 b4 b3 b2 b1 b0 83h w tsl b7 b6 b5 b4 b3 b2 b1 b0 83h r tsc b7 b6 b5 b4 b3 b2 b1 b0 84h r/w target0 target minute (bcd) 85h r/w target1 target second (b cd) 86h r/w target2 target fram (bcd) 87h r/w dactl da0en ctlsel acu1 acu0 qctl3 qctl2 qctl1 qctl0 88h r/w feactl lecas lref mrcd sdbs sbck cas8b frcdb edoen 89h r/w dffcntl 1 1 ffht2 dffht1 dffht0 dfflt2 dfflt1 dfflt0 8ah r/w atctl dxoff udta udt1 ud t0 uclks reft1 reft1 reft0 8ch w sta0m crcokm ilsynm nosynm lblkm wshortm sblkm bin0m uceblkm 8dh w sta1m 0 0 0 hderam 0 0 0 shderam 8eh w sta2m 0 0 0 0 0 nocorm rferam 0 8fh w sta3m 0 0 ecfm 0 0 0 c2dfm 0 90h r/w apcnf apen apien demand apins apin1 a pin0 apout1 apout0 91h r/w apfmt apfmt7 apfm6 apfmt5 apfmt4 apfmt3 apfmt2 aptm1 apfmt0 92h r/w apbkl b7 b6 b5 b4 b3 b2 b1 b0 93h r/w apbkh test test apacenb test 0 0 0 b8 94h r/w apwcl 97h
preliminary/confidential subject to change without notice w88227f/W88227QD - 36 - 1999/10/1 rev: 0.70 95h r/w apwch 04h 96h r/w apvol lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 97h w apack data unused 98h w puctl hip1 hip0 uip1 uip0 rip1 rip0 hd7upb apipb 9ah r/w bicctl bicen atmsen blimen blims rclim3 rclim2 rclim1 rclim0 9bh w buflim b7 b6 b5 b4 b3 b2 b1 b0 9bh r bufc b7 b6 b5 b4 b3 b2 b1 b0 9ch r/w acc tl atten acmen tcincen atlim4 atlim3 atlim2 atlim1 atlim0 9dh r/w tcc b7 b6 b5 b4 b3 b2 b1 b0 9eh r/w skipc b7 b6 b5 b4 b3 b2 b1 b0 9fh r/w ttc b7 b6 b5 b4 b3 b2 b1 b0
preliminary/confidential subject to change without notice w88227f/W88227QD - 37 - 1999/10/1 rev: 0.70 ir - index register the decoder index register is latched from up port - 0 by the bu illt - in 74373 at the falling edge of internal ale signal. the high byte address of decoder register is defined by ccsa0 (40h) with default value 40h. : decoder register read (read ver) mov dptr,#0401ah movx a,@dptr : decoder register wri te (set ccsa1 as 0xc0h) mov a,#0c0h mov dptr,#04041h movx @dptr,a pfar - packet fifo access register - (read 00h) while scod (20h.2) is high, the atapi command packet issued from host is received by the 12 - byte packet fifo. flag tendb (01h.r6) and fpkt (30h.r1) are used to check if the packet fifo is full. the microprocessor can read the atapi command packet by repeatedly read register pfar (00h,r) . once the fifo becomes empty, the value ffh will be returned if microprocessor read pfar. the packet fifo can also be used to receive command parameter less than 12 bytes. first, the control bit scod (20h.2) is set high to select the packet fifo to be addressed by the atapi data port. when drq (37h.3) changes from 0 to 1, the lower 4 bits of atblo (34h) is latched as the fifo threshold. upon the number of bytes in the fifo reaches the threshold, flag tendb (01h.r6) becomes active - low and flag fpkt (30h.r1) becomes active - high. once fpkt becomes high, any data writes to the atapi data port is rejected. in tctl - interrupt control register - (write 01h, read 11h) bit 7: pfneen - packet fifo not empty interrupt enable if this bit is high, decoder interrupt activates when pfneb (01h.r7) becomes active - low. this bit is clear to 0 after master reset, firmware re set. bit 6: tenden - transfer end interrupt enable if this bit is high, decoder interrupt activates when tendb (01h.r6) becomes active - low. this bit is also automatically enabled if the host issues the packet command (opcode a0h) while hiien (2eh.w7) is h igh and drive is selected. this bit is clear to 0 after master reset, firmware reset. bit 5: srien - sector ready interrupt enable if this bit is high, decoder interrupt activates when srib (01h.r5) becomes active - low. this bit is clear to 0 after master reset, firmware reset and decoder reset. bit 4: reserved
preliminary/confidential subject to change without notice w88227f/W88227QD - 38 - 1999/10/1 rev: 0.70 bit 3: pffscb - packet fifo full trigger status completion enable if this bit is low and ascen (18h.5) is high, the autmatic status completion is performed after the end of data transfer into packet fifo. this bit is clear to 0 after master reset, firmware reset. bit 2: reserved bit 1: dten - data transfer enable set this bit high enables the data transfer logic. this bit should be set before trigger any data transfer. in order to reduce the inte rference of microprocessor, this bit is also automatically enabled during the following operation: trigger adtt (17h.w2) host issues packet command (opcode a0h) while apkten (18h.7) is enabled and drive is selected in case of un - recoverable transfer error, setting this bit low will terminate the current data transfer immediately. bit 0: reserved intrea - interrupt reason register - (read 01h) bit 7: pfneb - packet fifo not empty interrupt flag this bit becomes active - low after packet fifos receive any dat a issued by the host through atapi data port. decoder interrupt is activated when this bit becomes active - low if pfneen (01h.w7) is enabled. this flag and intterupt is deactivated after the last byte is read by microprocessor through register pfar (00h,r ) . bit 6: tendb - transfer end interrupt flag this bit becomes active - low at the end of data transfers. flag tdir (30h.r5) and fpkt (30h.r1) can be used to determine which type of transfer end occurs. decoder interrupt is activated when this bit becomes active - low if tenden (01h.w6) is enabled. tendb (01h.r6) tdir (30h.r5) fpkt (30h.1) transfer end reason interrupt acknowledge register 0 1 0 data - in transfer dhtack (0eh), tack (07h) 0 1 x data - out transfer tack (07h) 0 0 x a0 command packet transfer tack (07h) bit 5: srib - sector ready interrupt flag if rmsri (5ch.0) is low, this bit is used to indicate that one sector is ready to be accessed. if rmsri (5ch.0) is high, this bit is generated only by staerr (80h.r6) , bin0 (80h.r5), dsfuli (80h.r4) , lastbk (80h.r3) , ltti (80h.r2) , tnfi (80h.r1) or hcei (80h.r0) . reading register stat3 (0fh,r) or tarsta (80h,r) deactivates this flag and its corresponding interrupt.
preliminary/confidential subject to change without notice w88227f/W88227QD - 39 - 1999/10/1 rev: 0.70 bit 4: hcib - host command interrupt flag this bit is activated by the following eve nts: (1) host set bit srst in atapi device control register, if hiien(2eh.7) is enabled. this event also activates flag srst (2fh.r7). the interrupt is acknowledged by master reset, reading atcmd (37h) or setting clrbsy (20h.4) high. (2) host issues command ot her than packet and device reset command to this drive, if drive is selected and hiien(2eh.7) is enabled. this event also activates flag atac (2fh.6) . this flag and interrupt is acknowledged by master reset, reading atcmd (37h) or setting clrbsy (20h.4) high. (3) host issues execute drive diagnostics command, if hiien(2eh.7) is enabled. this event also activates flag diag (2fh.r6). this flag and interrupt is acknowledged by master reset, reading atcmd (37h) or setting clrbsy (20h.4) high. (4) host issues command to a non - exist slave drive, if shien(2eh.2) is enabled. this event also activates flag shdc (2fh.r4). this flag and interrupt is acknowledged by master reset, reading atcmd (37h) or setting clrbsy (20h.4) high. (5) host issues device reset command, if arstie n(2fh.1) is enabled. this event also activates flag arst (2fh.r3). this flag and interrup is acknowledged by writing any value to arstack (30h,w). bit 3: tbsyb - transfer busy flag this bit becomes active - low when the data transfer to host is triggered by the following events: writing any value to register thtrg (06h,w) setting bit adtt (17h.w2) high after host read the last byte to be transferred, this flag is deactivated. bit 2: apib - audio playback interrupt flag if apout (90h,1 - 0) are not zero, th is bit is used as audio - playback - interrupt flag. if apien (90h.6) is high, this bit activats whenever the playback of one block is finished, the corresponding interrupt is acknowledged by writing any value to apack (97h,w). bit 1: dfrdyb - data fifo read y after data transfer is triggered, the 32 - byte data fifos is automatically filled. this bit is used to indicate that the data fifos is ready to be read by the host for debugging. the data fifo is automatically cleared in any of the following conditions: chip reset, host reset and firmware reset dten (01h.w1) is 0 dinb (1fh.w1) is 1 dfrst (2bh.w3) is 1 the end of data - in transfer
preliminary/confidential subject to change without notice w88227f/W88227QD - 40 - 1999/10/1 rev: 0.70 bit 0: scib - subcode interrupt flag if scien (2ch.w4) is enabled, this bit becomes active - low when one of the following event s occurs: iss (22h.r0) becomes active - high nesbk (22h.r1) becomes active - high mss (22h.r2) becomes active - high when subcode interrupt is activated, the microprocessor can read register substa (22h,r) to determine the reason of interrupt. writing register sciack (22h,w) deactivates this flag and its corresponding interrupt. twcl - transfer word counter low - (read/write 02h) before triggering data transfer, the number of words to be transferred should be set through 12 - bit transfer word counter (twc). the number of words minus 1 should be written to this counter while using standard atapi 16 - bit data transfer. after host read one word, the counter is decreased by one. transfer end interrupt flag , tendb (01h.r6) , is activated when this counter becomes zero . bit 7 - 0: twch[7:0] - transfer word count low twch - transfer word counter high - (read/write 03h) bit 7: latxf - linear address transfer enable if this bit is high, the linear address transfer is enabled. in this case, the data stored from the ddress specified by rac (2dh,1dh,1ch) are transferred to host after trigger. the size of transfer data is limited by twc (03h/02h) . if this bit is low, the block - offset transfer is enabled. in this case, the data stored from the address specified by tbh/l (25h/2 4h) and tach/l (05h/04h) are transferred to host after trigger. the address of data warps around at the block boundary, so the size of transfer data is limited by block size. bit 3 - 0: twch[3:0] - transfer word count high tacl/tach - transfer address cou nter - (write 04h/05h) before triggering block - offset data transfer, the external ram address of data to be transferred should be set through tach/l (05h/04h,w) . this number in this counter specifies the first available data address relative to the beginn ing of the block. the block number should also be specified through transfer block registers tbh/l (25h/24h) . after one word is read by host, tach/l are incremented to the next available data address. the following equation illustrates the relation betw een block - offset and linear address: linear address = (block number block size) + address offset
preliminary/confidential subject to change without notice w88227f/W88227QD - 41 - 1999/10/1 rev: 0.70 thtrg - transfer to host trigger register - (write 06h) this register is used to trigger data transfer regardless of what value is written. if dinb (1fh .1) is low, triggering this register automatically fills the data fifo and then flag dfrdyb (01h.r1) becomes active - low when the data fifo becomes ready. if dinb (1fh.1) is high, data - out transfer is enabled, e.g., parameter of mode - select command. a mor e convenient way is set adtt (17h.w2) high and then trigger hardware data transfer sequence. tack - transfer acknowledge - (write 07h) writing any value to this register deactivates flag tendb (01h.r6) and its corresponding interrupt. head0 to head3 - header registers - (read 03h to 07h) these four registers are used to hold the information of header bytes of each sector. header registers should be read soon after stavab (0fh.r7) becomes active - low. note that the header bytes are distrustful if wrong mode is set while ecc is enabled. if bit shden (0bh.w0) is enabled, registers head0 - 3 are used to hold subheader bytes instead. if control bit qmsf (80h.w4) is set high, the corresponding msf bytes in q - channel information would be automatically loaded in to head0 - 2 (04h - 06h,r) when each byte is ready from dsp. the register head3 (07h,r) hold first byte of q - channel (control and adr) or 0xffh if crc checking of q - code is erroneous. bial/biah - buffering initial address - (write 08h/09h) the rule for conf iguration is that the first byte of the sector is stored at biah/l(09h/08h) - 0ch before enabling the external ram buffering through ctrl0 (0ah,w) , biah/l should be set to control the location of the first byte follows data sync for each data sector. the ram block for buffering is controlled by the number in registers ddbh/l(29h/28h) plus one.
preliminary/confidential subject to change without notice w88227f/W88227QD - 42 - 1999/10/1 rev: 0.70 bacl, bach - buffering address counter - (read 0ah/0bh) - obsolete eial/eiah - ecc initial address - (read 08h/09h, write 0ch/0dh) - obsolete ctrl0 - control r egister 0 - (read/write 0ah) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: decen - decoding logic enable setting this bit high enables the decoding logic. bit 6: rtedc - real time edc checking enable setting this bit high enables the real - time - edc - checking logic. the rspc error correction is performed only when the result of real time edc check is error. bit 5: edcen - error detect and correct enable setting this bit high enables the ecc and edc logic. change of this bit takes effect after next sync. bit 4: acen - automatic correction enable if both m2rq (0bh.w3) and this bit is high, the type of error correction is automatically determined by form bit in the subheader byte. if only m2rq (0bh.w3) is high, the typ e of error correction is controlled by f2rq (0bh.w2) . if m2rq (0bh.w3) is low, this bit does not affect the correction of mode 1 data. bit 3: pktinh - obsolete bit 2: bufen - buffering enable setting this bit high enables incoming dsp data buffering. whe n this bit is high, the values of register head (04h - 07h) and subh (14h - 17h) are retrieved from external ram rather than from incoming serial data. when bufen is low, any setting of qcen or pcen is meaningless. change of this bit takes effect after next sync.
preliminary/confidential subject to change without notice w88227f/W88227QD - 43 - 1999/10/1 rev: 0.70 bit 1: qcen - q - codeword correction enable when this bit is high, q - codeword rspc correction logic is enabled. change of this bit takes effect after next sync. bit 0: pcen - p - codeword correction enable when this bit is high, p - codeword rspc correc tion logic is enabled. change of this bit takes effect after next sync. decen 0ah.7 bufen 0ah.2 edcen 0ah.5 qcen 0ah.1 pcen 0ah.0 decoder mode operation flow remark 1 1 1 1 1 q - p correction q ? p ? crc 1 1 1 1 0 q - correction q ? crc 1 1 1 0 1 p - corre ction p ? crc 1 1 1 0 0 buffer - only crc 1 1 0 0 0 buffer - only no crc check for m2f2 data without edc 1 0 0 0 0 disk - monitor no buffering 0 x x x x decoder disable no operation note that if atmsen (9ah.6) is high, the decoder logic will operate in disk - monitor mode before the target is found. when the target is found, the setting of register ctrl1 (0bh,w) will be automatically loaded into decoder logic. ctrl1 - control register 1 - (read/write 0bh) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: sien - sync insertion enable when this bit is high, the sector boundary is determined by internal sync insertion logic. bit 6: sden - sync detection enable when this bit is high, the sector boundary is determined by sync bytes of incoming serial data. this bit should not set for reading cd - da data. bit 5: dscren - descramble enable setting this bit is high enables the descramble logic. this bit should not set for reading cd - da data. bit 4: cwen - corrected data wr ite enable setting this bit high enables corrected data to be written to the external ram. this bit is normally set when correction is enabled by qcen (0ah.w1) or pcen (0ah.w0) . bit 3: m2rq - mode 2 ecc request setting this bit to high enables the cd - rom xa mode 2 correction logic. yellow book mode 1 correction will be performed if this bit is low.
preliminary/confidential subject to change without notice w88227f/W88227QD - 44 - 1999/10/1 rev: 0.70 bit 2: f2rq - form 2 request setting this bit high request the data to be processed by the cd - rom xa mode - 2 form - 2 format if m2rq (0bh.3) is high. if m2rq (0bh.3) is high and this bit is low, the cd - rom x1 mode - 2 form - 1 correction will be performed. this bit is not effective if acen (0ah.w4) is high. bit 1: mcrq - mode byte check request when this bit is high, ecc logic will check the 4th header byte with t he setting of m2rq (0bh.3) to determine if ecc correction to be performed. bit 0: shden - subheader switch enable when this bit is high, registers head (04h - 07h,r) are used to provide subheader bytes. disc format sien (0bh.7) sden (0bh.6) descre n (0bh.5) cwen (0bh.4) m2rq (0bh.3) f2rq (0bh.2) cd - da 1 0 0 0 0 0 yellow book mode 1 1 1 1 1 0 0 yellow book mode 2 1 1 1 0 0 0 cd - rom xa m2f1 1 1 1 1 1 0 cd - rom xa m2f2 1 1 1 x 1 1 stat0 - status register 0 - (read 0ch) bit 7: crcok - cyclic redundancy ch eck ok this bit is used to indicate that the cyclic redundancy check of the latest available sector is passed. bit 6: ilsyn - illegal sync pattern if sden (0bh.w6) is high, this bit becomes high when a sync pattern is detected less than 2352 bytes after l ast sync pattern was detected/inserted. bit 5: nosyn - no sync pattern if sien (0bh.w7) is high, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted. bit 4: lbkf - long block flag if sien (0 bh.w7) is low, this bit becomes high when a sync pattern is not detected at 2352 bytes after last sync pattern was detected/inserted. bit 3: wshort - word short this bit becomes high when the incoming serial data rate is too high to be processed. bit 2: s bkf - short block flag if sden (0bh.w6) is low, this bit becomes high when a sync pattern is detected less than 2352 bytes after last sync pattern was detected/inserted.
preliminary/confidential subject to change without notice w88227f/W88227QD - 45 - 1999/10/1 rev: 0.70 status flag sien (0bh.7) sden (0bh.6) internal operation ilsyn(0ch.6) x 1 re - synchr onize internal sync logic nosyn(0ch.5) 1 x internal sync logic provide internal sector boundary lbkf(0ch.4) 0 x internal sync logic do not provide internal sector boundary sbkf(0ch.2) x 0 do not re - synchronize internal sync logic bit 1: reserved bit 0 : uebk - uncorrectable errors in block this bit is used to indicate that at least one data is corrected in the latest available data block. stat1 - status register 1 - (read 0dh) bit 7 - 5: bi[2:0] - raw block indicator bit 4: hdera - header erasure this bit is high if there is at least one erasure flag detected in header bytes excluding mode byte. erasure in mode byte will cause rmod (0eh.r7 - 4) all become high. bit 0: shdera - subheader erasure this bit is high if erasure flags are detected for both byte s in at least one subheader byte - pairs. erasures are latched from pin c2po it bufen (0ah.w2) is disabled. otherwise, header and subheader bytes are retrieved from external ram while the following sector is being buffered. dhtack - dram to host transfer acknowledge - (write 0eh) writing dhtack, regardless of what data is written, deactivates tendb (01h.r6) that caused by data - in transfer. stat2 - status register 2 - (read 0eh) bit 7 - 4: rmod[3:0] - raw mode bit rmod2 - 0 are directly latched from bit 2 - 0 from the 4th header byte and rmod3 is high if any one of the other 5 bits in the mode byte is high. rmod3 is also high if a mode byte erasure is detected. bit 3: mode2 - mode 2 selected flag this bit reflects the setting of m2rq (0bh.w3) .
preliminary/confidential subject to change without notice w88227f/W88227QD - 46 - 1999/10/1 rev: 0.70 bit 2: nocor - no correction if ecc logic is enabled by bit edcen (0ah.w5) , and qcen (0ah.w1) or pcen (0ah.w0) , this bit becomes high if ecc logic is interrupted the followings: cwen (0bh.w4) is disabled. mode mismatch is detected while mcrq (0bh.w1) is enabled. mode e rasure is detected while mcrq (0bh.w1) is enabled. a mode erasure occurs if the incoming c2po flag is set for the fourth header byte, indicating unreliable mode data. form 2 enabled while ecc logic is set to mode 2. form 2 blocks should not be corrected. form 2 can be enabled by control bit f2rq (0bh.w2), or by the form bit in the subheader byte if acen (0ah.w4) is enabled. form bit erasure while ecc logic is set to mode 2 and acen is enabled. a form bit erasure is detected if the incoming c2po flags are set for both form bits in the subheader bytes. ilsyn (0ch.r6) becomes high while sden (0bh.w6) is enabled bit 1: rfera - raw form erasure this bit becomes high when a form bit erasure was detected. a form bit erasure is detected if the incoming c2po flag s are set for both form bits in the submode bytes (bit 5 in byte 18 and 22). rfera becomes valid when srib (01h.r5) becomes active - low, and remains valid until the next block sync. bit 0: rform - raw form bit this bit is high if the form bit is high in th e submode bytes of the incoming serial data. this bit becomes valid when flag srib (01h.r5) becomes active - low, and remains valid until the next block sync. frst - firmware reset register - (write 0fh) writing this register, regardless of what value is written, trigger a firmware reset. flag frst (2fh.r1) is set by firmware reset. stat3 - status register 3 - (read 0fh) bit 7: stavab - obsolete, may return 0 or 1 bit 5: ecf - error corrected flag this bit is used to indicate that there is at least on e byte was corrected in the latest available block. bit 1: c2df - c2 detected in block flag if c2wen (10h.w2) is high, c2df becomes high when there is at least one c2po flag was detected in the previous block. bit 6,4,3,2,0: reserved
preliminary/confidential subject to change without notice w88227f/W88227QD - 47 - 1999/10/1 rev: 0.70 ctrlw - control - wr ite register - (write 10h) this register is 0 after chip reset, host reset, firmware reset and decoder reset. bit 7: reserved bit 6: swen - synchronized write enable if this bit is high, the change of bufen (0ah.w2) will be synchronized to the end of next sector sync. the buffering of c2po flags is also controlled by this bit if c2wen (10h.w2) and bufen (0ah.w2) are both enabled. this function prevents buffering of an incomplete block. bit 5: sdss - subcode and dsp sync synchronization this bit provides sy nchronization of cd - da format data. if this bit is high, the writing of incoming serial data to the external ram will start at the first left - channel lower - byte following the end of subcode block. note that this bit should not be used when subcode logic is not enabled. bit 4: dcken - dsp clock enable if this bit is high, clock from dsp is used by internal decoder logic. dcken should be set high before decen (0ah.w7) is set high. bit 3,0: reserved bit 2: c2wen - c2 flag write enable if this bit and bufen (0ah.w2) are both high, the c2 flags of incoming serial data will be latched into the external ram. this operation is synchronized to the end of sync if swen (10h.w6) is high. bit 1: eccrst - ecc logic reset trigger setting this bit to high resets decodi ng logic, including: srien (01h.w5) ? 0 ctrl0 (0ah,w) ? 00h ctrl1 (0bh,w) ? 00h stat0 - 2 (0ch - 0eh,r) ? 00h stat3 (0fh,r) ? 80h tarsta (80h,r) ? 00h eccrst is automatically cleared by itself. bit 0: dsprst - dsp interface reset trigger setting this bit to high resets dsp interface. dsprst is automatically cleared by itself.
preliminary/confidential subject to change without notice w88227f/W88227QD - 48 - 1999/10/1 rev: 0.70 crtrg - correction retry trigger - (write 11h) writing register crtrg, regardless of what data is written, triggers the decoding logic to perform another correction sequence to the s ame block. bit 7 - 1: reserved bit 0: crrl - correction retry register load setting this bit high while writing register crtrg (11h,w) re - loads the setting of edcen (0ah.w5) , qcen (0ah.w1) , or pcen (0ah.w0) to decoding logic. decoder parameter updated at the end of sync updated by writing crrl edcen (0ah.w5) yes yes qcen (0ah.w1) yes yes pcen (0ah.w0) yes yes acen (0ah.w4) yes no bufen (0ah.w2) yes no m2rq (0bh.w3) yes no f2rq (0bh.w2) yes no mcrq (0bh.w1) yes no mbtc0 - multi - block transfer contr ol 0 - (read/write 12h) the host interface supports multi - block transfer without microprocessor intervention by following sequence: mbc (12h.4 - 0) ? the number of block to be transferred minus 1 (ex. 3) twch/l (03h/ - 2h) ? the number of words to be transferr ed in each block minus 1 (ex. 1175) tach/l (05h/04h) ? the starting point of the block (ex. f4h, ffh) tbh/l (25h/24h) ? the ram block number of the first block to be transferred (ex. 5) atbhi/lo (35h/34h) ? the total bytes to be transferred (ex. 9408) adtt (17h.w4) ? 1 ps: stwcen (18h.3) should not be set in multi - block transfer operation. when adtt is set, host will receive hirq, check status, and then start to read data.
preliminary/confidential subject to change without notice w88227f/W88227QD - 49 - 1999/10/1 rev: 0.70 after the last word of one block (except the last one) is read by the host, the foll owing hardware sequence is executed: twch/l (03h/02h) ? reload tach/l (05h/04h) ? reload tbh/l (25h/24h) ? auto - increment mbc0 (12h.4 - 0) ? auto - decrement flag tendb (01h.r6) only becomes active at the end of data transfer of the last block. this register is 0 after chip reset, host reset and firmware reset. 3 2 1 0 n n+1 n+2 n+3 5 6 7 9 mbc(12h.4-0) tbh/l(25h/24) data transfer tendb(01h.r6) hirq transfer trigger status complete twc/tac reload twc/tac reload twc/tac reload 8 bit 7: mbvab - multi - block counter valid flag this bit is used to indicate that mbc (12h.4 - 0) is stable enough to be monitored by microprocessor. there is no need to moni tor this bit in normal operation. bit 6: mbinc - multi - block increment flag this bit becomes active - high if microprocessor sets incmbc (13h.w0) and multi - block number increment has not completed. there is no need to monitor this bit in normal operation. bi t 4 - 0: mbc[4:0] - multi - block counter before triggering multi - block transfer, the number of blocks to be transferred minus 1 should be written to mbc (12h.4 - 0) . single block transfer is performed if mbc (12h.4 - 0) is zero. there is no need to monitor thi s counter normal operation.
preliminary/confidential subject to change without notice w88227f/W88227QD - 50 - 1999/10/1 rev: 0.70 mbtc1 - multi - block transfer control 1 - (read/write 13h) this register is for debug only. this register is 0 after chip reset, host reset and firmware reset. bit 7 - 3: reserved bit 2: mbtien - multi - block transfer interrupt enable if mbtien and mbtfen are both enabled, decoder interrupt will activate at the end of data transfer of each block if the block count in mbc (12h.4 - 0) is not zero. there is no need to set this bit in normal operation. bit 1: mbtfen - multi - block tran sfer interrupt flag enable if this bit is high, mbti (30h.r4) will be activated at the end of data transfer of each block if the block count in mbc (12h.4 - 0) is not zero. there is no need to set this bit in normal operation. bit 0: incmbc - increment multi - block counter setting this bit high increments mbc (12h.4 - 0) . this function is useful in data transfer to host by dma mode. because data byte count is not specified in dma mode transfer, the number of block to be transferred can be incremented when a new block becomes available before the transfer is completed. ectrl - enhanced control register - (write 14h) bit 7 - 2: reserved bit 1: ir7f - provide flag utby at ir7 when this bit is high, flag utby (1fh.r7) can be monitored by read bit - 7 of the index r egister. bit 0: disai - disable auto - increment of microprocessor - ram address counter when this bit is high, the automatic increment of the rac (2dh/1dh/1ch) address counter is disabled. note that disai should be 0 before rftrg (2ah.w6) is triggered. sub h0 to subh3 - subheader registers - (read 14h to 17h) these registers are used to hold the information of subheader bytes. if bufen (0ah.w2) is disabled, subheader bytes are latched from incoming serial data. if bufen (0ah.w2) is enabled, subheader bytes are retrieved from the external ram.
preliminary/confidential subject to change without notice w88227f/W88227QD - 51 - 1999/10/1 rev: 0.70 evtrg - event trigger register (write 16h) the following bits will clear themselves after the triggered operation are completed. these bits should not be set while decen (0ah.7) is high to avoid conflict with normal target increment on end of crc - checking. bit 7 - 2: reserved bit 2: tarinc7 - target registers increment 7 trigger setting this bit high increments the target (84h - 86h) by 7. bit 1: tarinc - target registers increment trigger setting this bit high increme nts the target (84h - 86h) by 1. bit 0: tardec - target registers decrement trigger setting this bit high decrements the target (84h - 86h) . astrg - automatic sequence trigger register (write 17h) the following bits will clear themselves after the triggered operation are completed. bit 7: reserved bit 6: csrt - clear soft reset trigger setting this bit high clears bit srst in the atapi device control register. bit 5: dsct - disk seek complete trigger if abyen (18h.1) is high, setting dsct high triggers the following operations: set bsy dsc (37h.4) ? 1 clear bsy if abyen (18h.1) is low, setting dsct high sets dsc(37h.4) to 1. bit 4: sigt - atapi signature trigger setting this bit high initialize the task registers with atapi signature. atfea (31h) ? 00 h aterr (31h) ? 01h atint (32h) ? 01h atspa (33h) ? 01h atblo (34h) ? 14h atbhi (35h) ? ebh atsta (37h) ? x00x0000b note that register atdrs (36h) is not cleared by triggering sigt to abide by the atapi protocol.
preliminary/confidential subject to change without notice w88227f/W88227QD - 52 - 1999/10/1 rev: 0.70 bit 3: cpft - clear packet fifo trigger setting this bit high clears the packet fifo. bit 2: adtt - automatic data transfer trigger if pio (1fh.2) is high, setting adtt high triggers the following pio data transfer sequence: set bsy dten (01h.w2) ? 1 scod (20h.2) ? 0 if dinb (1fh.1) is 0; otherwise, 1 atint (32h) ? 02h if dinb (1fh.1) is 0; otherwise, 00h if stwcen (18h.w3) is enabled, then atbhi/lo ? (twch/l + 1) 2 the data transfer logic will start to fill the data fifo automatically. the following sequence will be ex ecuted when dfrdyb (01h.r1) become active - low: drq (37h.3) ? 1 clear bsy hirq (2eh.3) ? 1 after detecting the interrupt, the host will check the status and then read the data. stwcen (18h.3) should not be used for automatic multiple block transfer. in stead, atblo, atbhi should be set by firmware to: (mbc + 1) ((twc + 1) 2) if pio (1fh.2) is low, setting adrtg high triggers the following dma data read sequence: set bsy dten (01h.w1) ? 1 scod (20h.2) ? 0 if dinb (1fh.1) is 0; otherwise, 1 atin t (32h) ? 02h if dinb (1fh.1) is 0; otherwise, 00h bit 1: drqt - drq trigger if bit pio (1fh.2) is high, setting this bit high triggers the following hardware sequence: drq (37h.3) ? 1 bsy ? 0 hirq (2eh.3) ? 1 when bit pio is low (dma mode), this bi t should not be triggered.
preliminary/confidential subject to change without notice w88227f/W88227QD - 53 - 1999/10/1 rev: 0.70 bit 0: sct - status completion trigger setting this bit high triggers the following hardware sequence: check (37h.0) ? acheck (3eh.0) corr (37h.2) ? acorr (3eh.2) drdy (37h.6) ? adrdy (3eh.6) atint (32h) ? 03h clear bsy hirq (2eh.3) ? 1 apkten (18h.7) ? 1, if autoen (18h.4) is high ascen (18h.5) ? 0 after detecting the interrupt, the host reads the atapi status register and if necessary, the error register for the command completion status. asctrl - automatic se quence control register - (read/write 18h) bit 7: apkten - automatic packet transfer enable setting this bit high enables automatic packet transfer logic. when apkten is high, the following hardware sequence is performed if host issues opcode a0h to the a ta command register if drive has been selected: set bsy (37h.7) apkt (30h.r0) ? 1 clear packet fifo aterr (31h) ? 00h atint (32h) ? 01h dten (01h.w1) ? 1 tenden (01h.w6) ? 1, if hiien (2eh.7) is high s cod (20h.2) ? 1 check (37h.0) ? 0 corr (37h.2) ? 0 drq (37h.3) ? 1 dsc (37h.4) ? 1, if asdsc (3dh.4) is high drdy (37h.6) ? 1 hirq (2eh.3) ? 1, if a0ien (18h.0) is high apkten ? 0 clear bsy (37h.7) atac (2fh.w6) will not be activated during automatic packet transfers.
preliminary/confidential subject to change without notice w88227f/W88227QD - 54 - 1999/10/1 rev: 0.70 when the drive becomes ready after bsy is cleared, the host starts to issue 12 - byte atapi command packet. reception of the 6th packet word activates the following events. fpkt (30h.r1) ? 1 tendb (01h.r6) ? 0 pin uintb activate if tenden (01h.w6) has been enabled writing any value to regist er tack (07h) deactivates apkt, tendb, and corresponding interrupt. bit 6: adcen - automatic drq clearing enable when this bit is high, drq (37h.3) is cleared to 0 and bsy (37h.7) is set to 1 after the end of following transfers: host reads from external ram host writes to command packet fifo bit 5: ascen - automatic status completion enable when this bit is high, status completion is performed after the end of the following transfers: host reads from external ram host write data to packet fifo, if pffscb (01h.w3) is low adcen (18h.6) should be enabled when ascen is enabled to provide clearing of drq (37h.3) and setting of bsy (37h.7). if both adcen and ascen are enabled, the following hardware sequence is executed at the end of one of the above data tran sfers: set bsy drq (37h.3) ? 0 check (37h.0) ? acheck (3eh.0) corr (37h.2) ? acorr (3eh.2) drdy (37h.6) ? adrdy (3eh.6) atint (32h) ? 03h clear bsy hirq (2eh.3) ? 1 apkten (18h.7) ? 1, if autoen (18h.4) is high ascen (18h.5) ? 0 after detecting the interrupt, the host reads the atapi status register and if necessary, the error register for the command completion status. this bit is also cleared by setting sct (17h.w0) high. bit 4: autoen - automatic apkten set after status completion enable when thi s bit is high, apkten (18h.7) will be set after automatic status completion sequence triggered by either sct (17h.0) or ascen (18h.5).
preliminary/confidential subject to change without notice w88227f/W88227QD - 55 - 1999/10/1 rev: 0.70 bit 3: stwcen - set transfer word count enable when this bit is high, the value (twch/l + 1) 2 is loaded into atblo an d atbhi when adtt (17h.2) is triggered and pio (1fh.2) has been set high. if acmen (9ch.6) is not enabled, control bit stwcen should not be set for multiple block transfer. instead, atbhi/lo should be set by firmware to : (mbc4 - 0 + 1) (twch/l + 1) 2 . bit 2: aucrcen - automatic ultra dma crc error logic enable if aucrcen (18h.2) is set high, the automatic status complete logic would be stopped if ucrcokb (30h.r3) is high. if no crc error has occurred in last ultra dma burst, status complete sequence wo uld be automatically executed. this bit should be set high only if ascen (18h.5) is set high as well. this bit is automatically clear when: (1) automatic status complete sequence is triggered or (2) sct (17h.w0) is set high. bit 1: abyen - automatic bsy set enable when this bit is high, the following sequence is executed when disk seek complete is triggered by dsct (17h.w5) : set bsy dsc (37h.4) ? 1 clear bsy dsct ? 0 bit 0: a0ien - a0h command interrupt enable if this bit is high and apkten (18h.7) has been enabled, hirq (2eh.3) becomes active - high after an opcode a0h is issued to ata command register. cctl0 - clock control register 0 - (write 19h) this register is 0 after chip reset. bit 7: ckstp - clock stop setting his bit high stops the internal clock. ckstp is de - activated by the following events: master reset or firmware reset command write from the host while the drive is selected host issues diagnostic command, regardless of drive selection host issues command to shadow drive if shdrv (3fh.6 ) is enabled host set bit srst in atapi device control register high, regardless of drive selection bit 6 - 4: reserved bit 3 - 0: cks[3:0] - clock skew control cks3 - 0 are used to control the duty cycle of the internal clock. the low period of cycle increases as the skew value increments.
preliminary/confidential subject to change without notice w88227f/W88227QD - 56 - 1999/10/1 rev: 0.70 cctl1 - clock control register 1 - (write 1ah) this register is 0 after chip reset. bit 7,6: obsolete bit 5: xininv - inverted xin as system clock when this bit is high, the internal system clock is inverted from crystal in put . bit 4: psken - programmable system clock enable when this bit is high, the frequency of internal system clock is controlled by register pskctl (59h). bit 3,2: clk[1:0] - obsolete bit 1: reserved bit 0: xtald2 - crystal divided by 2 the internal clock frequency is half of crystal frequency if this bit is high. ver - version register - (read 1ah) this register is used to hold the version number. dspsl - dsp selection register - (write 1bh) bit 7: c2ml - c2 msb to lsb when this bit is high, the sequ ence of erasures via pin c2po/sdata2 is from msb to lsb. bit 6: s16o - select 16 offset the incoming serial data is latched one clock after pin lrck changes if this bit is high. bit 5: lchp - left channel polarity the incoming serial data is latched as l eft channel when pin lrck is high if this bit is high. bit 4: sft8 - shift 8 clocks the incoming serial data is latched by delay 8 clocks if this bit is high. bit 3: d2en - sdata2 enable setting this bit high configures pin c2po/sdata2 as second serial d ata input. bit 2: sel16 - select 16 bits per channel the incoming serial data is latched 16 times per channel if this bit is high. bit 1: dir - data direction setting this bit high selects the direction of data from pin sdata from msb to lsb. bit 0: edg e - latching edge select setting this bit high selects the rising edge of bck for latching data from pin sdata .
preliminary/confidential subject to change without notice w88227f/W88227QD - 57 - 1999/10/1 rev: 0.70 c2beb - c2 block error byte - (read 1bh) the block error byte is the or of all the c2 error flag bytes. racl, rach, and racu - ram address counter - (write 1ch, 1dh, 2dh) these three registers are used to set linear address of the external ram. before accessing registers ramrd/ramwr or triggering linear - address transfer, microprocessor should set these registers. the microprocessor should w rite the ram starting address into the counter while busy flag utby (1fh.r7) is low. then this counter increases automatically each time when a byte is read or written. ramwr - ram write register - (write 1eh) to gain access to external ram, the micropr ocessor should first wait for flag utby (1fh.r7) to become low, then set the address through raclu/h/l(2dh/1dh/1ch) . writing data into register ramwr triggers the following sequence: data is transferred from the microprocessor to register ramwr. data is tr ansferred from ramwr to the ram located by the address counter. increments racl, rach, and racu increments by one clear flag utby ramrd - ram read register - (read 1eh) to gain access to external ram, the microprocessor should first wait for flag utby (1 fh.r7) to become low, then set the address through raclu/h/l (2dh/1dh/1ch) . writing data into register ramrd triggers the following sequence: data previously stored in ramrd is transferred to the microprocessor. ram data located by the address counter is transferred to the ramrd register. increments racl, rach, and racu increments by one clear flag utby note that the first data read from ramrd is invalid.
preliminary/confidential subject to change without notice w88227f/W88227QD - 58 - 1999/10/1 rev: 0.70 hictl0 - host interface control register - (write 1fh) bit 7 - 6: reserved bit 5: h16s - (obso lete) no matter what value is set, the data transfer between host and decoder is using 16 - bit protocol. bit 4: laen - latch enable if this bit is high, host address and chip - select signals will be latched when pins n hrd or n hwr change from high to low . bit 3: mdma - multi - word dma mode setting this bit to high enables multi - word dma mode if pio (1fh.2) is low. bit 2: pio - pio/dma mode select setting this bit high causes data transfer to/from host using pio mode. this bit is also controlled by bit - 0 o f atfea (1f1h/171h) if asmda (5bh.7) is high. bit 1: dinb - data - in transfer enable setting this bit low select data - in transfer. otherwise, the data - out transfer is enabled. bit 0: udma - ultra dma enable setting this bit high selects data transfer pro tocol as ultra dma. the bandwidth of ultra dma depends on the system frequency and the setting of udt1 - 0 (8ah.5 - 4) . hictl0 (1fh,w) data - in data - out pio mode xxxx x10xb xxxx x11xb mdma mode x8h xah udma mode x9h xbh stat5 - status register 5 - (r ead 1fh) bit 7: utby - microprocessor to ram transfer busy when the microprocessor - to - ram transfer is not complete, this bit is high. bit 6 - 4: reserved bit 3: mdma - multi - word dma mode bit 2: pio - pio/dma mode select bit 1: dinb - data - in transfer enabl e bit 0: udma - ultra dma enable
preliminary/confidential subject to change without notice w88227f/W88227QD - 59 - 1999/10/1 rev: 0.70 hictl1 - host interface control register - (write/read 20h) the value in this register is 26h after chip reset. bit 7 : reserved bit 6: pdiagen - pin npdiag enable setting this bit high causes pin npdiag to the active - lo w state. pdiagen is automatically de - activated, causing pin npdiag to be high - impedance, by the following events: reception of execute drive diagnostics command (ata opcode 90h) reception of ata soft reset (srst) master reset bit 5: daspen - pin ndasp en able setting this bit high activates pin ndasp . daspen is automatically de - activated, causing pin ndasp to be high - impedance, by the following events: reception of execute drive diagnostics command (ata opcode 90h) reception of ata soft reset (srst) mast er reset this bit is also controlled by dasps2 (3fh.2), dasps1 (3fh.1) and daspss (3fh.0). bit 4: clrbsy - clear bsy setting this bit high causes the flag bsy in the atapi status register to become low if apkt (30h.r0) is not high. this bit is self - clear after the bsy is clear. bit 3: setbsy - set bsy setting this bit high causes the flag bsy in the atapi status register to become high if apkt (30h.r0) is not high. this bit is self - clear after the bsy is set. bit 2: scod - select command - packet - fifo or da ta the data received from atapi data port is stored in packet fifo if this bit is high. this bit is also controlled by adtt (17h.w2) and apkten (18h.7) . bit 1: rdyen - pin iordy enable setting this bit high enables iordy (pin 49) to work with hrdb (pin 5 0). bit 0: io16en - pin iocs16b enable setting this bit high allows pin iocs16b to become active - low when 16 - bit data access is in use. this bit should be enabled in normal operation.
preliminary/confidential subject to change without notice w88227f/W88227QD - 60 - 1999/10/1 rev: 0.70 sictl0 - subcode interface control register 0 - (read/write 21h) bit 7 - 6: reserved bit 5: ascend - alternative subcode end timing if this bit is high, the timing of subcode end interrupt is delayed to end of subcode sync. otherwise, the subcode end interrupt is generated at start of subcode sync. this bit is 0 after reset . bit 4: qsigen - signature on qcrcok enable if this bit is high, the signature 0xffh is written to dram with block offset 9e0h if crc checking of q - code is erroneous. this bit is 0 after reset. bit 3: pqenb - p - data or q - data enable bits 7 and 6 of subcod e data are written to the external ram if this bit is low. bit 2 - 0: subcs[2:0] - subcode clock select if sbck (88h.3) is low and sctc (5ah.w) is zero, these bits are used to select subcode clock rate. sciack - subcode interrupt acknowledge - (write 22h) writing any value to this register de - activates scib (01h.r0) if scien (2ch.w4) is enabled. substa - subcode status register - (read 22h) when scib (01h.r0) is activated, the microprocessor can read this register to determine the reason of interrupt. th ese register is clear to 0 by reading substa (22h.r). bits 7 - 5: reserved bit 4: qcrcok - q - channel crc ok flag if q - channel extraction is enabled, this bit reflects the status of crc checking of q - channel information. bit 3: reserved bit 2: mss - missing subcode sync a missing - subcode - sync sets mss high and negates scib (01h.r0). a microprocessor interrupt is activated also if scien (2ch.w4) is enabled. bit 1: nesbk - normal end of subcode block a normal - subcode - block - end sets nesbk high and negates scib (01h.r0) . a microprocessor interrupt is activated also if scien (2ch.w4) is enabled. bit 0: iss - illegal subcode sync an illegal - subcode - sync sets iss high and negates scib (01h.r0) . a microprocessor interrupt is activated also if scien (2ch.w4) is ena bled.
preliminary/confidential subject to change without notice w88227f/W88227QD - 61 - 1999/10/1 rev: 0.70 tbh/l - transfer block register - (read/write 25h/24h) if latxf (03h.7) is low, tbh/l form a 9 - bit counter that is used to specify the first ram block to be transferred, while registers tach/l (05h/04h,w) specify the starting address relative to t he beginning of this ram block. the block - offset transfer is carried within a transfer ring that is controlled by dtrch/l (53h/52h) and dtrbh/l (51h/50h) . the buffer ring and transfer ring are usually defined in the same range. note that tbh/l (25h/24h) do not increment automatically at the end of each transfer unless: dinb (1fh.1) is low (data - in transfer is enabled) latxf (03h.7) is low (block - offset transfer is used) if acmen (9ch.6) is high, tcc (9dh) minus n and tbh/l (25h/24h) plus n right after ski pc (9eh) is set n . if bicen (9ah.7) is high and bcfsel (9ah.5) is low, the dsp buffering stop when buffering block (internal) reach tbk (9bh,w) . scbh/l - subcode block register - (read/write 27h/26h) scbh/l (27h/26h) form a 9 - bit counter that contains th e block number of the latest available subcode data that can be read by the host. the number in scbh/l (27h/26h) plus 1 points to the ram block that is buffering incoming subcode. the number in scbh/l (27h/26h) increments at the end of subcode block buffer ing. if sdbs (88h.4) is high, the buffering of subcode is controlled by ddbh/l (29h/28h) rather than scbh/l (27h/26h) . ddbh/l - decoded data block register - (read/write 29h/28h) ddbh/l(29h/28h) form a 9 - bit counter that contains the number of the lates t available decoded data block after decoder interrupt occurs. cd - rom sector data buffering is a block - based ring operation. in real - time - correction (rtc) mode, i.e., bicen (9ah.7) is low, if the number in ddbh/l (29h/28h) is n - 1 , then the current sec tor is buffered into block with number n . the ddbh/l (29h/28h) increments at each sync. when the decoded - block - number equals the value in wbrch/l (57h/56h) , the sector is buffered into the block with number specified by wbrbh/l (55h/54h) . in buffer - indep endent - correction (bic) mode, i.e., bicen (9ah.7) is low, ddbh/l (29h/28h) increments at the end of edc - checking if there is no staerr (80h.r6) or hcei (80h.r0) error.
preliminary/confidential subject to change without notice w88227f/W88227QD - 62 - 1999/10/1 rev: 0.70 ramcf - ram configuration register - (read/write 2ah) this register is 0 after chip r eset. bit 7: rftyp - refresh type the refresh mode of dram is cas - before - ras if this bit is high. the refresh mode of dram is ras - only if this bit is low. bit 6: rftrg - ram filling trigger setting this bit high triggers the dram filling. all locations i n the external ram will be filled with the value in register ramwr (1eh,w) . the value (ex:00h) should be written to registers racl, racu, and rach before triggering rftrg. flag rfc (2ah.r5) will change from 0 to 1 when all ram locations have been filled . after ram filling has completed, the microprocessor should clear rftrg to 0. bit 5: rfc - ram fill completion flag (read only) this flag will change from 0 to 1 when all ram locations have been filled with the value in register ramwr (1eh,w) . this flag is clear when rftrg is disabled. bit 5: reserved (write only) bit 4: swap - host high - low swap setting this bit high causes the host access of high/low byte to be swapped. bit 3: twes - two we/cas select if this bit is low, pin cash/nrweh is used as colu mn address strobe for high byte. if this bit is high, pin cash/nrweh is used as write enable strobe for high byte.. bit 2 - 0: rtc[2:0] - external ram type configuration bits the external ram should be appropriately configured by these three bits according to its specification. rtc[2:0] are de - activated by master reset, but are not changed by firmware reset. rtc[2:0] ram configuration 0,1, 4, 7 reserved 2 256k x 4 - bit x 2, 256k x 8 - bit x 1, 128k x 8 - bit x 1, 8 - row 9 - column 3 128k x 8 - bit x 1, 9 - row 8 - col umn 4 64k x 16 - bit x 1, (8 - row 8 - column) 128k x 16 - bit x 1 (9 - row 8 - column) 128k x 8 - bit x 2 (9 - row 8 - column) 5 256k x 16 - bit x 1 128k x 16 - bit x 1 (8 - row 9 - column) 128k x 8 - bit x 2, (8 - row 9 - column)
preliminary/confidential subject to change without notice w88227f/W88227QD - 63 - 1999/10/1 rev: 0.70 memcf - memory layout configuration register - (w rite 2bh) bits 7 - 6: reserved bits 5 - 4: dbaf[1:0] ? obsolete these two bits must be set 0. bit 3: dfrst - data fifo reset setting this bit high resets data fifo. this bit is not self - clear. bit 2: frdy - fast pin iordy enable setting this bit high accele rates the de - assertion of pin iordy without referring pin nhrd . bit 1 - 0: rlc[1:0] - external ram layout configuration bits the memory layout configuration should be set as shown in the following table: rlc[1:0] block size 0,1 -- 2 c00h 3 a00h the bl ock size should be set as c00h if c2wen (10h.w2) is enabled. sictl1 - subcode interface control register 1 - (write 2ch) bit 7: sbxck - subcode external clock the external clock from pin exck is used by the subcode logic if this bit is high. bit 6: scen - subcode enable setting this bit high enables the subcode logic. bit 5: cd2sc - clock divided by 2 for subcode logic the subcode clock is divided by two if this bit is high. bit 4: scien - subcode interrupt enable setting this bit high enables subcode interrupts. bit 3: exinv - external clock invert select if exop (2ch.w2) is high, setting this bit high selects an inverted clock output at pin exck . bit 2: exop - pin exck operation setting this bit high sets pin exck as an output.
preliminary/confidential subject to change without notice w88227f/W88227QD - 64 - 1999/10/1 rev: 0.70 bit 1 - 0: scf[1:0] - subcode format select scf[1:0] subcode format 0 smd0 (philips) 1 smd1 (eiaj - 1) 2 smd2 (eiaj - 2) 3 reserved rasta - dram address status register - (read 2dh) pin ra7 - 0 are input with weak pull - up during master reset or when rtc (2ah.2 - 0) is 000b. r a7 - 4 are used as power - on setting and ra3 - 0 can be used as general input when rtc (2ah.2 - 0) is 000b. the status of ra7 - 0 can be read from rasta (2dh,r) . misc0 - miscellaneous control register 0 - (write 2eh) bit 7: hiien - host interface interrupt enabl e setting this bit high enables the microprocessor interrupt of the host interface. host interface interrupt occurs at the following conditions: srst (device control register) is written as 1 after 0 to either master or slave drive. execute drive diagnost ics command is written to either master or slave drive. any opcode is written to the atapi command register while the drive is selected except: (1) command opcode is 08h, (2) command opcode is a0h and apkten (18h.7) is high. ide interface interrupt is cle ared by the following: master reset reading register 37h writing 1 to clrbsy (20h.4) bit 6: reserved bit 5: drveb - drive selection enable setting this bit low enables selection of the drive if bit drv in atapi drive select register matches the setting of mdrv (2eh.4) . bit 4: mdrv - master drive setting this bit high sets the drive to be selected when bit drv in the atapi drive select register is set to 0 (master drive).
preliminary/confidential subject to change without notice w88227f/W88227QD - 65 - 1999/10/1 rev: 0.70 bit 3 : hirq - host interrupt request set this bit high asserts interrupt at pin hirq if the drive is selected and nien is enabled in the atapi device control register. hirq is also automatically set by the following: automatic packet transfer sequence, enabled by apkten (18h.7) automatic status completion sequence, enabled by sct (17h.w0 ) or ascen (18h.5) hirq is automatically de - activated by the following: master reset set bit srst in the atapi device control register high host issue ata command while the drive is selected host read atapi status register while the drive is selected bit 2: shien - shadow command interrupt enable setting this bit high enables the microprocessor interrupt for the shadow command. signal uintb becomes low - active when shdc (2fh.r5) becomes high - active if this bit is enabled. bit 1, 0: reserved miss0 - misce llaneous status register 0 - (read 2eh) bit 5: srub - status register updated flag this bit becomes high when the atapi status register is updated by the following: microprocessor writes to 37h microprocessor triggers dsct (17h.w5) microprocessor triggers sct (17h.w0) automatic status completion occurs if ascen (18h.5) is enabled reception of a0h command if apkten (18h.7) is enabled master reset bit 4: mdrvf - master drive flag this bit is high if the drive is configured as master. this bit is low if the drive is configured as slave. bit 3: hintf - host interrupt flag this bit reflects the status of the source of pin hirq . bit 2: nien - bit nien in device control register this bit reflects the value of bit nien in atapi device control register. bit 1: npdiag - pin npdiag flag this bit reflects the status of pin npdiag . bit 0: ndasp - pin ndasp flag this bit reflects the status of pin nda sp .
preliminary/confidential subject to change without notice w88227f/W88227QD - 66 - 1999/10/1 rev: 0.70 misc1 - miscellaneous control register 1 - (write 2fh) this register is 0 after chip reset. bit 7: arrc - atapi register read control when this bit is high, the atapi registers can be read regardless of the value of bsy if the drive is selected. bit 6: sarrc - shadow drive atapi register read control when this bit is high, the shadow atapi registers can be read reg ardless of the value of bsy if the shadow drive is selected. bit 5 - 4: hrsts[1:0] - obsolete bit 3: arsten - arst enable when arsten is high, internal signal arstb becomes active - low if host writes an device reset command (opcode 08h) and reset the chip. bi t 2: arsts - arstb timing select arsten arsts type function of arstb remark 1 0 od arstb (reset - mode) 1 1 od arstb (interrupt - mode) in interrupt - mode, writing any value to register arstack (30h,w) de - activates arstb. in reset - mode, arstb automaticall y de - activates itself after 256 system clocks. bit 1: arstien - atapi soft reset interrupt enable when this bit is high, uintb becomes active - low whenever host writes an device reset command (opcode is 08h). bit 0: arwc - atapi register write control host writes to atapi registers (except device control register) will not take effect when arwc and bsy are high, if bsy is not set by the following commands: opcode 90h is written to ata command register while the drive is selected. opcode 90h is written to a ta command register while the shadow drive is selected if shdrv (3fh.6) if high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 67 - 1999/10/1 rev: 0.70 miss1 - miscellaneous status register 0 - (read 2fh) bit 7: srst - soft reset flag this bit becomes high when host writes 1 to bit srst in the atapi device control register if either master or slave drive is selected. when srst becomes high, the following events will be executed: bsy (37h.7) ? 1 initialize atapi signature pdiagen (20h.w6) ? 0 and disables pin npdiag (43) to high - impedance state disable pin nda sp (37) to h igh - impedance state if daspss (3fh.0) is low. negates pin nda sp (37) if daspss (3fh.0) is high. ckstp (19h.7) ? 0 activates host interrupt to the microprocessor if hiien (2eh.w7) is high. hirq (2eh.w3) ? 0 host interrupt is cleared by read register atcm d (37h) or write clrbsy (20h.4) . srst is de - activated by read register miss1 (2fh,r) after srst is set to low by host. bit 6: atac - atapi command if the drive is selected, this bit becomes high when any command is written to the atapi command register ex cept the following opcode are received. opcode is 90h opcode is 08h and either arst1 (2fh.w3) or arstien (2fh.w1) is enabled opcode is a0h and apkten (18h.w7) is high atac is de - activated by the following: master reset reading register atcmd (37h) writing 1 to clrbsy (20h.4) bit 5: diag - execute drive diagnostics command this bit becomes high if execute drive diagnostics command (opcode 90h) has been written to either master or slave drive. meanwhile, the following events will be executed: bsy(37h.7) ? 1 pdiagen (20h.w6) ? 0 and disables pin npdiag to high - impedance state ckstp (19h.7) ? 0 atapi error register ? 01h atapi feature register ? 00h atapi interrupt reason register ? 01h atapi sam tag byte ? 01h atapi byte counter register low/high ? 00h ata pi drive select register ? 00h clear atapi status register except bit bsy and service activates host interrupt to the microprocessor if hiien (2eh.w7) is enabled
preliminary/confidential subject to change without notice w88227f/W88227QD - 68 - 1999/10/1 rev: 0.70 bit 4: shdc - shadow command flag this bit becomes high when the host writes a command to a n on - existent slave drive. meanwhile, decoder interrupt becomes low - active if shien (2eh.w2) is enabled. atac is de - activated by the following: master reset reading register atcmd (37h) writing 1 to clrbsy (20h.4) bit 3: arst - atapi soft reset flag this bi t becomes high when device reset command (opcode 08h) is written to either master or slave drive. arst is de - activated by writing any value to register arstack (30h,w). bit 2: rst - reset flag this bit is high when the chip is currently being reset by chi p reset, host reset, or firmware reset. bit 1: frst - firmware reset flag this bit is high if the current or most recent reset was firmware reset. the first read of register miss1 (2fh,r) following the end of the firmware reset clears this flag to 0. bit 0: mrst - master reset flag this bit is high if the current or most recent reset was activated by master reset. the bsy flag is set whenever master reset is activated. the first read of register miss1 (2fh,r) following the end of the master reset clears this flag to 0. arstack - atapi soft reset acknowledge (write 30h) writing any value to this register triggers the following events: clears flag arst (2fh.r3) deactivates arstb signal if arsten (2fh.w3) and arsts(2f.w2) are both high deactivates pin uin tb if arstien (2fh.w1) is enabled miss2 - miscellaneous status register 0 (read 30h) bit 7: srstd - soft reset with drq this bit becomes high if host activates srst in the atapi device control register while drq is high and the drive is selected. this bit is updated at rising edge of srst.
preliminary/confidential subject to change without notice w88227f/W88227QD - 6 9 - 1999/10/1 rev: 0.70 bit 6: cmdc - command conflict this bit becomes high if one of the following events occurs while bsy is high: host writes any opcode to atapi command register while drive is selected. host writes any opcode to atapi command register while shadow drive is selected and shdrv (3fh.6) is enabled. host writes opcode 90h (execute drive diagnostics) to atapi command register. cmdc is updated each time the host writes the atapi command register. bit 5: tdir - data transfer direction tendb (01h.r6) tdir (30h.r5) fpkt (30h.1) transfer end reason acknowledge register acknowledge result 0 1 0 data - in transfer dhtack (0eh) tdir is clear to 0 0 1 x data - out transfer tack (07h) tdir is celar to 0 and fpkt is unchanged 0 0 x a0 c ommand packet transfer tack (07h) this flag is cleared by writing dhtack (0eh) or writing tack (07h) . bit 4: mbti - obsolete bit 3: ucrcokb - ultra dma crcok/ram parity interrupt flag this bit becomes high if an ultra dma crc error is detected at the en d of ultra dma burst. this flag is clear to low by reading miss2 (30h.r) . bit 2: crst - chip reset flag this bit is set high by chip reset. the first read of register miss2 (30h,r) following the end of the chip reset clears this flag to 0. bit 1: fpkt - f ull packet flag this bit becomes high if the host has written the number of data bytes indicated in register atblo (less than 12 bytes), or the host has written a 12 - byte command packet. if cod (32h.0) is low when drq (37h.3) change from 0 to 1, the count in atblo is latched as a threshold value for fpkt logic. if cod is high when drq (37h.3) change from 0 to 1, the threshold value of fpkt logic is set as 12. whenever the number of bytes in the packet fifo equals the threshold value, flag fpkt becomes h igh. to receive data from host using packet fifo, cod (32h.0) and atblo (32h) should be updated at rising edge of drq. bit 0: apkt - automatic packet transfer flag this bit is set to 1 when host writes opcode a0h to ata command register if drive is select ed and apkten (18h.7) has been enabled. when this flag is high, bsy is controlled by the automatic packet transfer logic. hence, setting of clrbsy (20h.4) and setbsy (20h.4) is of no effect. apkt is de - activated by writing any value to register tack (0 7h,w) . apkt is de - activated by master reset but is not changed by firmware reset.
preliminary/confidential subject to change without notice w88227f/W88227QD - 70 - 1999/10/1 rev: 0.70 aterr - atapi error register (write 31h/read 39h) this register is set as 01h by the following events: master reset srst execute drive diagnostics command triggering sigt (17h.w4) atfea - atapi feature register (read 31h) this register is de - activated by the following events: master reset srst execute drive diagnostics command triggering sigt (17h.w4) atint - atapi interrupt reason register (read/write 32h) this registe r is set as 01h by the following events: master reset srst execute drive diagnostics command triggering sigt (17h.w4) atspa - atapi sam tag bytes register (read/write 33h) this register is set as 01h by the following events: master reset srst execute dri ve diagnostics command triggering sigt (17h.w4)
preliminary/confidential subject to change without notice w88227f/W88227QD - 71 - 1999/10/1 rev: 0.70 atblo - atapi byte count low (read/write 34h) this register is set as 14h by chip reset, host reset, srst or triggering sigt (17h.w4) . this register is set as 00h by execute drive diagnostics command. a tbhi - atapi byte count high (read/write 35h) this register is set as ebh by chip reset, host reset, srst or triggering sigt (17h.w4) . this register is set as 00h by execute drive diagnostics command. atdrs - atapi drive select (read/write 36h) this re gister is set as 00h by the following: master reset srst execute drive diagnostics command note that this register is not changed by triggering sigt (17h.w4) . atsta - atapi status register (write 37h/read 38h) this register is set as x0000000b by chip re set, host reset. this register is set as x00x0000b by srst, execute drive diagnostics command, or triggering sigt (17h.w4) .note that bsy is not changed by writing register atsta (37h). atcmd - atapi command register (read 37h) this register is used to l atched the command opcode written from host without default value.
preliminary/confidential subject to change without notice w88227f/W88227QD - 72 - 1999/10/1 rev: 0.70 assta - atapi shadow status register - (write 38h) bit 0: scheck - shadow check bit if configured as a master drive, the firmware should set scheck following each host write to atcmd to comply with atapi specification. bit - 7 of shadow status register is the same as bsy of status register. bit 6 - 1 of shadow status register are all 0s. scheck is de - activated by chip reset, host reset, or host writes to command register regardless of whi ch drive is selected. aserr - atapi shadow error register - (write 39h) bit 2: sabrt - shadow abrt bit the microprocessor should set sabrt following each host write to atcmd to comply with atapi specification if configured as a master drive. the other bits of shadow error register are all 0s.. lddbl/lddbh - latched decoded data block register - (read 3ah/3bh) the decoded data block number in ddbh/l is latched into lddbh/l at the end of edc check. this number is available to the end of next edc check. the lddbh/l should not be used if bicen (9ah.7) is enabled. apksta - status register for automatic packet transfer - (write 3dh) bit 4: adsc - disk seek complete for automatic packet transfer the value of adsc is the value of bit dsc in atapi status r egister during automatic packet command transfers. ascsta - status register for automatic status completion - (write 3eh) bit 6: adrdy - drive ready for automatic status completion the value of adrdy is the value of bit drdy in the atapi status register during automatic status completion. bit 2: acorr - correctable error for automatic status completion the value of acorr is the value of bit corr in the atapi status register during automatic status completion. corr is de - activated by chip reset, host res et, or firmware reset. bit 0: acheck - check for automatic status completion the value of acheck is the value of bit check in the atapi status register during automatic status completion. check is de - activated by chip reset, host reset, or firmware reset.
preliminary/confidential subject to change without notice w88227f/W88227QD - 73 - 1999/10/1 rev: 0.70 shdctl - shadow drive control register (read/write 3fh) bit 7, 4, 3: reserved bit 6: shdrv - shadow drive enable if mdrv (2fh.4) is high, the bit reflects the level on pin nda sp until shdrvl (3fh.5) is set high. if this bit is high, shadow register su pport for the non - existent slave drive is enabled.. bit 5: shdrvl - shadow drive enable latch microprocessor should set this bit high at least 450 milliseconds after master reset to latch the setting of shdrv (3fh.6) from pin nda sp if configured as a maste r drive. this bit is 0 after chip reset and host reset. bit 2: dasps2 - dasp select 2 setting this bit high enables daspen (20h.w5) during host reset. dasps2 should normally be 0 to comply with atapi specification. this bit is 0 after chip reset. bit 1: dasps1 - dasp select 1 setting this bit high enables daspen (20h.w5) following end of host reset. this bit is 0 after chip reset. bit 0: daspss - dasp srst select setting this bit high enables daspen (20h.w5) following the end of soft reset (srst). this bi t is 0 after chip reset and host reset. ccsa0 - configurable chip select base address register 0 (read/write 40h) the content of this register is used as the base address of decoder chip select. the default of this register after hardware reset is 0x4 0h. ccsa1 - configurable chip select base address register 1 (read/write 41h) the content of this register is used as the base address of ccs1. the default of this register after hardware reset is 0x00h. ccsa2 - configurable chip select base addre ss register 2 (read/write 42h) the content of this register is used as the base address of ccs2. the default of this register after hardware reset is 0x00h.
preliminary/confidential subject to change without notice w88227f/W88227QD - 74 - 1999/10/1 rev: 0.70 glctl1 - global control register 1 (read/write 43h) the default of this register after hardwa re reset is 0x00h. bit 7: rsto - pin rsto output control the state of pin nrsto is the inverse value of this control bit. this bit is 0 after chip reset. bit 4: up323s - pin up323 selection up323s (43h.4) pin up32/up33 internal decoder interrupt remark 0b int0 int1 (default) 1b int1 int0 bit 2: ckostp: pin cko output stop setting this bit high immediately puts the output of pin cko at a steady "high" state. this bit is low after master reset. bit 1: aclks - aclk source selection setting this bit high select pin dxi as aclk input source. setting this bit low select pin uxi as aclk input source. this bit is 0 after chip reset. bit 0: dclks - dclk source selection setting this bit high select pin dxi as dclk input source. setting this bit low select pin u xi as dclk input source. this bit is 0 after chip reset. lsta0 - 3 (read 48h - 4bh) - obsolete lhd0 - 3 (read 4ch - 4fh) - obsolete ring control registers - (read/write 50h to 57h) these eight registers add flexibility to the block control of external memory that is controlled by rtc2 - 0 (2ah.2 - 0) initially. once one of these eight registers is set, all eight registers should be set to take full control of block configuration of the external memory. the data - transfer - ring and write - buffer - ring are normally s et the same value. dtrbl/dtrbh - data transfer ring base register - (read/write 50h/51h) data transfer ring base register and data transfer ring ceiling register treat the external memory as a ring while transferring data to the host. data transfer ring base register specifies the base block number of this ring.
preliminary/confidential subject to change without notice w88227f/W88227QD - 75 - 1999/10/1 rev: 0.70 dtrcl/dtrch - data transfer ring ceiling register - (read/write 52h/53h) data transfer ring base register and data transfer ring ceiling register treat the external memory as a ring while tran sferring data to the host. data transfer ring base register specifies the ceiling block number of this ring. the first block to be transferred is specified by registers tbh/l (25h/24h) . the further data transfer after the end of data transfer ceiling bl ock will access data in data transfer base block. wbrbl/wbrbh - write buffer ring base register - (read/write 54h/55h) write buffer ring base register and write buffer ring ceiling register treats the external memory as a ring while buffering the serial data from dsp. write buffer ring base register specifies the base block number of this ring. wbrcl/wbrch - write buffer ring ceiling register - (read/write 56h/57h) write buffer ring base register and write buffer ring ceiling register treats the extern al memory as a ring while buffering the serial data from dsp. write buffer ring base register specifies the base block number of this ring. the first block to be buffered is specified by registers ddbh/l (29h/28h) . further serial data buffering after th e end of write buffer ceiling block will buffer serial data into the write buffer base block. tccctl - tcc source control register (read/write 58h) this register is 00h after mater reset. this register controls the increment/decrement source of tcc (9d h). bit 7 - 4: reserved bit 3 - 2: tccctl[3:2] tccctl[3:2] function 00h tcc increment by cbk increment default 01h tcc increment by apbk increment bit 1 - 0: tccctl[1:0] tccctl[1:0] function 00h tcc decrement by tbk increment default 01h tcc decrement by apbk increment
preliminary/confidential subject to change without notice w88227f/W88227QD - 76 - 1999/10/1 rev: 0.70 pskctl - programmable system clock control register - (read/write 59h) this register should be set before the programmable system clock is enabled by setting psken (1ah.w4) high. this register is 0 after master reset. bit 7: psktest ( write only) - programmable system clock test enable this bit is low after master reset and should be set low in normal operation. setting this bit high is only used for factory test. bit 7: locked (read) - programmable system clock locked this bit is hig h once the internal system clock is ever on lock with the programmed frequency. bit 6: locksel (write) - programmable system clock lock select if this bit is high, the internal system clock will keep the same delay path once the programmed frequency is loc ked. this function keeps system clock at steady frequency, but the frequency may be affected by temperature. if this bit is low, the internal system clock will be continuously adjusted to fit the programmed frequency according to crystal input and result in a various frequency. bit 6: pskexe (read only) - programmable system clock extreme condition this bit is low after master reset. the bit is high when the programmable system clock is at its lowest or highest frequency. this indicates that the freque ncy equation, according to psk (59h.5 - 0), may not effective in this case. bit 5 - 0: psk[5:0] - programmable system clock factor if psken (1ah.w4) and psksel (59h.w7) are high, these six bits are used to controlled the internal system frequency. the equati on is: frequency of system clock = frequency of xin (psk[5:0] + 2) ? 16 sctc - subcode timer control register - (write 5ah) if sbxck (2ch.w7) and cd2sc (2ch.w5) are both low, the clock used by subcode logic clock is controlled by subcs2 - 0 (21h.w2 - 0) un less any non - zero value is written into this register. the value of this register should be calculated as follows: ( n + 2 ) tc dsf = 11.3 / 2 where tc is the internal clock period(ex: 50ns for 20mhz crystal), dsf is the disk speed factor(ex: 4 for 4 - fold speed drive). there is no need to set this register if sbck (88h.w3) is set high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 77 - 1999/10/1 rev: 0.70 efctl - enhanced feature control register - (read/write 5bh) bit 7: asdma - automatic set dma if this bit is high, the inverted value of dma bit of atfea (1f1h,w ) will be automatically loaded to pio (1fh.2) . this bit is 0 after chip reset, host reset and firmware reset. bit 6: obsolete bit 5: dsp1stb bit 4: reserved bit 3: alectl - ale input control if this bit is high, the ale input is gated with internal chip select signal. if this bit is low, the ale input latch the index register directly. bit 2: dspdw - dsp buffer double words enable if this bit is high, the dsp buffer is double - word - based; otherwise, it is word - based. this bit is 0 after chip reset, host r eset and firmware reset. bit 1: dra - direct register addressing enable this bit must be set high.. if this bit is set high, the direct register addressing function is enabled. this bit is 1 after chip reset in normal condition. bit 0: reserved efctl2 - enhanced feature control register 2 - (read/write 5ch) bit 7 - 4: reserved bit 3: ale2 - obsolete bit 2: syncp - sync bytes patch enable if this bit is high, the sync bytes of the following sector are patched to the previous sector. this bit must be disab led when reading cd - da data. bit 1: reserved bit 0: rmsri - remove frequent srib if rmsri (5ch.0) is high, flag srib (01h.r5) is generated only by flags staerr (80h.r6) , dsfuli (80h.r4) , lastbk (80h.r3) , ltti (80h.r2) , tnfi (80h.r1) or hcei (80h.r0) . set ting this bit high can reduce the overhead of microcontroller while the automatic cache management is used. this bit is 0 after chip reset, host reset and firmware reset.
preliminary/confidential subject to change without notice w88227f/W88227QD - 78 - 1999/10/1 rev: 0.70 giocf - general purpose i/o port configuration register (read/write 5dh) g4cf (5 dh.7 - 4) function nccs2 active (low) condition remark 0xxxb ra8 output is tri - state after master reset and is enabled when rtc (2ah.2 - 0) 1 000b default 10xxb gpio4 n/a 1100b nccs2 (p2 = ccsa2) 1101b nccs2 (p2 = ccsa2) & (p36 = "l") 1110b nccs2 (p2 = ccsa2) & (p37 = "l") 1111b nccs2 (p2 = ccsa2) & (p36 = "l" or p37 = "l") g2cf (5dh.3) daoen (87h.7) pin function remark 0b 0b nfce (default) 1b 0b gpio2 x 1b daout g3cf (5dh.2 - 0) function nccs1 active (low) condition remark 0xxb gpio3 n/a default 100b nccs1 (p2 = ccsa1) 101b nccs1 (p2 = ccsa1) & (p36 = "l") 110b nccs1 (p2 = ccsa1) & (p37 = "l") 111b nccs1 (p2 = ccsa1) & (p36 = "l" or p37 = "l") pskcnt - programmable system clock counter (read/write 5eh) this register is used fo r factory test.
preliminary/confidential subject to change without notice w88227f/W88227QD - 79 - 1999/10/1 rev: 0.70 gioctl - general i/o port control register - (read/write 5fh) this register is 0 after chip reset. bit 5: g4oen - general i/o port 4 output enable setting this bit high configure gio4 as output. otherwise, it is an input pin. bit 5: g 3oen - general i/o port 3 output enable setting this bit high configure gio3 as output. otherwise, it is an input pin. bit 5: g2oen - general i/o port 2 output enable setting this bit high configure gio2 as output. otherwise, it is an input pin. bit 4: g1oen - general i/o port 1 output enable setting this bit high configure gio1 as output. otherwise, it is an input pin. bit 3: gio4 - general purpose i/o port 4 if gio4 is configured as an input pin, the pin state can be read back from this bit. if gio 4 is configured as an output pin, set this bit low drive gio4 low and set this bit high cause a weak pull - up. bit 2: gio3 - general purpose i/o port 3 if gio3 is configured as an input pin, the pin state can be read back from this bit. if gio3 is configur ed as an output pin, set this bit low drive gio2 low and set this bit high cause a weak pull - up. bit 1: gio2 - general purpose i/o port 2 if gio2 is configured as an input pin, the pin state can be read back from this bit. if gio2 is configured as an outp ut pin, set this bit low drive gio2 low and set this bit high cause a weak pull - up. bit 0: gio1 - general purpose i/o port 1 if gio1 is configured as an input pin, the pin state can be read back from this bit. if gio1 is configured as an output pin, set t his bit low drive gio1 low and set this bit high cause a weak pull - up. tarctl - target control register - (write 80h) this register is used to control the automatic target search and header comparison. bit 7: targen - target function enable setting thi s bit high enables target search function but does not enable decoder simultaneously. the operation of target search is triggered by setting decen (0ah.w7) high. then the decoder generates first interrupt after the target sector, specified by target (84h - 86h) , is found. bit 6: dscen - decoding sector counting enable if dscen (80h.6) is enabled, flag dsfuli (80h.r4) becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc - checking.
preliminary/confidential subject to change without notice w88227f/W88227QD - 80 - 1999/10/1 rev: 0.70 bit 5: qen - q - channel extraction enable setting this bi t high enables q - channel extraction logic. this pin should be set high only when scen (2ch.w6) is high. once decoder and q - channel extraction are both enabled, the extracted q - channel bytes are written into the dram starting from offset 9e0h of each bloc k regardless of what mode of data is set. bit 4: qmsf - q - channel msf auto - load enable if q - channel extraction logic is enabled, setting this bit high enables the msf bytes of q - channel to be automatically loaded to head0 - 2 (04h - 06h,r) . the register head 3 (07h,r) hold first byte of data - q, (control and adr) or 0xffh if crc checking of q - channel is erroneous . bit 3: astopb - automatic decoder stop on error if this bit is low, decoder would automatically stop on the following conditions: hcei (80h.r0) act ivates if hceen (80h.w0) is enabled. tnfi (80h.r1) activates if tnfen (80h.w1) is enabled. ltti (80h.r2) activates if ltten (80h.w2) is enabled. lastbk (80h.r3) activates if blimen (9ah.5) is enabled dsfuli (80h.r4) activates if dscen (80h.w6) is enabled. staerr (80h.r6) activates if any status mask bit is enabled if this bit is low, the consistency of f/w and h/w should be carefully maintained. if this bit is high, the decoder is controlled by microprocessor. this bit is default low after chip reset. bit 2: ltten - larger than target interrupt enable setting this bit high enables ltti (80h.r2) to be reflected on srib (01h.r5) . bit 1: tnfen - target not found interrupt enable setting this bit high enables tnfi (80h.r1) to be reflected on srib (01h.r5) . bit 0: hceen - header compare error interrupt enable setting this bit high enables hcei (80h.r0) to be reflected on srib (01h.r5) . tarsta - target status register - (read 80h) this register is 0 after chip reset, host reset, firmware reset and decoder reset. reading this register deactivates srib (01h.r5) . bit 7: targed - target is found this bit is high after the target is found. bit 6: staerr - status error flag this bit becomes high if any status bit error, enabled by its corresponding mask bit, occ urs at the end of edc - checking. this flag is deactivated after reading register tarsta (80h,r) .
preliminary/confidential subject to change without notice w88227f/W88227QD - 81 - 1999/10/1 rev: 0.70 bit5: bin0 - block indicator is not zero flag if bin0m (8ch.w1) is high, this bit becomes high if the block indicator in head3 (07h.7 - 5) is not zero. this f lag also activates staerr (80h.r5) high. bit 4: dsfuli - decoding sector full interrupt flag if dscen (80h.6) is enabled, this flag becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc - checking. bit 3: lastbk - last decoded block if blim en (9ah.5) is high, this bit is set when the last pre - buffered block is decoded. firmware should disable decoder when detect this flag. the dsp buffering stop when buffer - cache full. bit 2: ltti - larger than target interrupt flag if ltten (80h.w2) and t argen (80h.w7) are high, this flag becomes high if the header larger than target when head0 - 2 (04h - 06h) are available. this flag is deactivated after reading register tarsta (80h,r). bit 1: tnfi - target not founded interrupt flag this bit becomes high if the headers in head0 - 2 (04h - 06h) never match the target after n successive comparisons. where n is the search limit number specified by tsl (83h,w ). if tnfen (80h.w1) is high, srib (01h.r5) activates when this bit becomes high. if astopb (80h.w3) is low, this event also clears decen (0ah.w7) and stop the decoder automatically. this flag is deactivated after reading register tarsta (80h,r) . the microprocessor could read out the header after event occurs to determine the distance from target. bit 0: hcei - header compare error interrupt flag after target is founded, the number in target (84h - 86h) will automatically increment after head0 - 2 (04h - 06h) are available. if the headers of following sector do not match the target, this bit becomes high and activate s srib (01h.r5) if hceen (80h.w0) is enabled. it also clears decen (0ah.w7) and stop the decoder automatically if astopb (80h.w3) is low. this flag is deactivated after reading register tarsta (80h,r) . dstl - decoding sector threshold register - (write 8 1h) if dscen (80h.w6) is enabled, this register specified the threshold number of successive sectors minus one to be decoded after header is targeted. flag dsfuli (80h.r4) becomes high when value in dscl (81h,r) is equal to dstl (81h,w) at the end of edc - checking. the initial value of dstl (81h,w) is ffh after chip reset, firmware reset and decoder reset. note that threshold value should not be set as 00h if dscen (80h.w6) is enabled. dsth - obsolete (write 82h)
preliminary/confidential subject to change without notice w88227f/W88227QD - 82 - 1999/10/1 rev: 0.70 dscl - decoding sector counter - (read 81h) once the target header is found, this counter increments when a sector is completely decoded. this counter is incremental - only, and the value follows ffh is 0. if dscen (80h.6) is high, flag dsfuli (80h.r4) becomes high if dscl (81h,r) is equal to dstl (81h,w) at the end of edc - checking. meanwhile, the decoder stops if astop b (80h.w3) is low. this register is cleared to 00h at the falling edge of decen (0ah,w7) . the initial value of dscl after chip reset, firmware reset and decoder reset is 00h . dsch - obsolete (read 82h) tsl - target search limit register - (write 83h) this register specified the limited number of target search. if n is the number specified by this register, tnfi (80h.r1) becomes high if the headers have not match the targe t after n successive sectors. since this register will not be changed by decoding operation, there is no need to writing it before every decoding operation. the initial value of tsl after chip reset, host reset and firmware reset is ffh. tsc - target s earch counter - (read 83h) after the decoder is enabled, the number of sectors has been searched can be monitored by reading tsc. this register is cleared to 00h at the falling edge of decen (0ah,w7) . the initial value of tsc after chip reset, firmware reset and decoder reset is 00h. target0 - target minute register - (read/write 84h) target1 - target second register - (read/write 85h) target2 - target frame register - (read/write 86h)
preliminary/confidential subject to change without notice w88227f/W88227QD - 83 - 1999/10/1 rev: 0.70 dactl - digital audio control register - (read/write 87h) this r egister is 00h after chip reset and host reset. bit 7: daoen - digital output enable if this bit is high, the digital audio data output through pin daout . bit 6: ctlsel - control bit source select if this bit is high, the 4 control bits of q channel are de fined by qctl3 - 0 (87h, 3 - 0) . otherwise, these 4 control bits are extracted from external ram. this bit is normal set low if the q - channel extraction work properly. bit 5 - 4: accu [1:0] - clock accuracy these two bits are used as clock accuracy bits in digit al audio output. these two bits are usually set 00b. bit 3:0: qctl [3:0] - control bits for q channel if ctlsel (87h.6) is high, these four bits are used as q channel control bits in digital audio output. feactl - feature control register - (read/write 88h) this register is 00h after chip reset and host reset. bit 7: lecas - latch data with external cas signal if this bit is high, input dram data is latched by external cash/l signal instead of rising edge of internal clock. this function can eliminate the timing difference between dram data and its latch signal caused by various internal chip delays, depending on circumstances. this bit should not be used if edoen (88h.1) is high. bit 6: lref - long refresh cycle if this bit is high, the tras is 2.5 clocks instead 1.5 clocks for refresh cycle. bit 5: mrcd - medium ras to cas delay the bit controls the timing of trcd and trp. if this bit is high the tras for ras - only refresh is 2 clocks and cas - before - ras is not affected (1.5 clocks). bit 4: sdbs - s ubcode and dsp block synchronization this bit provides block synchronization of cd - da format data. if this bit is high, the buffering of incoming serial data and subcode to the external ram will synchronize to the same block defined by ddbh/l (29h/28h) . b it 3: sbck - select bck as subcode clock when this bit is high, the pin bck is selected as subcode reference clock instead of system clock. this setting is suitable for drive using cav subcode. bit 2: cas8b - eight cas in one ras enable when this bit is set low, maximum the number of column address strobe is 8 instead of 4 in one dram fpm cycle.
preliminary/confidential subject to change without notice w88227f/W88227QD - 84 - 1999/10/1 rev: 0.70 bit 1: frcdb - fast ras to cas delay the bit controls the timing of trcd and trp. bit 0: edoen - edo dram support enable setting this bit enables edo dram su pport and the data latch timing of dram changes to falling edge instead of rising edge of internal clock. this bit should not be used if lecas (88h.7) is high. dffcntl - data fifo threshold control register - (read/write 89h) bit 7,6: reserved bit 5 - 3:` dffht[2:0] - data fifo high threshold when the number of bytes in data fifo larger than dffht, device stops pre - fetch to prevent fifo overrun. since the default setting of cas8b (88h.2) is low, the default value of dffht is 001b. dffht[2:0] threshold 0 00b 28 001b 24 default 011b 16 bit 2 - 0:`dfflt[2:0] - data fifo low threshold when the number of bytes in data fifo less than dfflt, device de - activates dmarq to prevent fifo underrun in traditional dma mode. when the number of bytes in data fifo less than dfflt, device would stop issuing dstrobe to prevent fifo underrun in ultra dma data - in mode. dfflt[2:0] threshold 000b 4 default 001b 8 011b 16
preliminary/confidential subject to change without notice w88227f/W88227QD - 85 - 1999/10/1 rev: 0.70 atctl - auxiliary timing control register - (read/write 8ah) this register is set 00h after chi p reset, host reset and firmware reset. bit 7: dxoff - dx crystal loop off setting his bit high can turn off the feedback loop beteween dxi and dxo and save power consumption. bit 6: udta - ultra dma timing acceleration if this bit is high, the internal ul tra dma base frequency is doubled from the clock sourxe that is selected by uclks (8ah.3) . bit 5 - 4: udt[1:0] - ultra dma timing control these two bits define the ultra dma timing factor, udtf , which control the timing of ultra dma transfer. tcyc = ( 2 + udtf ) tudma where tudma is clock period depends on setting of udta (8ah.6) and uclks (8ah.3) and tcyc is ultra dma cycle time (from dstrobe edge to dstrobe edge) device firmware should set udtf according to the clock source and the assigned ultra dma transfer mode after host issues set feature command. bit 3: uclks - ultra dma clock select if this bit is high, the clock source for udma is from pin aclk. if this bit is low, the clock source is system clock. bit 2 - 0: reft[2:0] - refresh timing control the frequency of refresh is controlled by reft2 - 0 (8ah.2 - 0) to support long refresh. the value after chip reset is 0. the refresh cycle defaults to be issued once after 256 system clocks. refresh period = 256 2reft system clock periods sta0m - statu s 0 mask register - (write 8ch) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 7 - crcok mask bit 6 - ilsync mask bit 5 - nosync mask bit 4 - lblk mask bit 3 - wshort mask bit 2 - sblk mask bit 1 - bin0 mask bit 0 - uceblk mask
preliminary/confidential subject to change without notice w88227f/W88227QD - 86 - 1999/10/1 rev: 0.70 sta1m - status 1 mask register - (write 8dh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 4: hdera mask bit 0: shder mask s ta2m - status 2 mask register - (write 8eh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 2: nocor mask bit 1: rfomr1 mask sta3m - status 3 mask register - (write 8fh) if any following bit is enabled, the flag staerr (80h.r6) becomes high when the corresponding status bit becomes active. bit 5: ecf mask bit 1: c2df mask apcnf - audio playback configuration register - (read/write 90h) the default value of this register is 00h after chip reset, host reset and firmware reset. bit 7: apen - audio playback enable setting this bit high enables audio playback logic. once audio playback logic is enabled, the buffered data will be sent out block after block starting from the setting o f apbk (92h/93h) . the playback stops immediately and keeps "mute" once this bit is set low. bit 6: apien - audio playback interrupt enable setting this bit high enables audio - playback - interrupt to be reflected on internal signal uintb whenever each block playback is finished. audio - playback - interrupt flag is reflected on apib (01h.r2) if apout1 - 0 (90h,1 - 0) is not zero. bit 5: demand - demand mode enable setting this bit high enable the demand mode. in demand mode, pin alrck is used as demand input. the abck clock is enabled only when demand is high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 87 - 1999/10/1 rev: 0.70 bit 4: apins - audio reference input select if this bit is set low, signal aclk is used as audio - playback reference clock. if this bit is high, sclk is used as audio - playback reference block. bit 3,2: api n[1:0] - audio input reference clock setting apin[1] apin[0] input reference clock 0 0 8.4672mhz 0 1 16.9344mhz 1 0 33.8688mhz 1 1 67.7376mhz the value in these registers should be properly set according to the audio - playback reference clock before en able apen (90h.7). bit 1,0: apout[1:0] - audio data output setting apout[1] apout[0] audio data output pin pin 6 pin 13 0 0 no output tri - state tri - state 0 1 nroe/asd abck alrck when apout are set zero, no output is generated from pin abck and pin alrck is used as left - right clock output. when apout are set not zero, flag apib (01h.r2) becomes low whenever one block audio - playback is finished. apfmt - audio playback format register - (read/write 91h) apfmt7 - 0 audio data format 000xx111h toshiba 001x x000h sanyo 101xx011h sony 48 - bit slot 110xx011h philip apfmt4 apfmt3 functions 0 0 normal stereo 0 1 mono left 1 0 mono right 1 1 left/right swap
preliminary/confidential subject to change without notice w88227f/W88227QD - 88 - 1999/10/1 rev: 0.70 apbkl/h - audio playback block register - (read/write 92h/93h) the bit - 0 of apbkh (93h) and bit7 - 0 of apbkl (92h) form a 9 - bit counter. the value in this 9 - bit counter defines the first block to be playbacked when apen (90h.7) is enabled. the value in these registers is incremented by 1 after one block playback is finished. 93h.bit - 7: test control - should be 0 93h.bit - 6: test control - should be 0 93h.bit - 5: apacenb - audio playback initial address counter latch enable if this bit is low, the value of wac (08h,09h) is loaded into internal register apac . the vaule of apac minus 12 is the starting a ddress of audio playback. 93h.bit - 4: test control - should be 0 apwcl/h - audio playback word count register - (read/write 94h/95h) the number in this counter plus one is the word count to be playbacked for each memory block. the default value of these registers is 0497 h after chip reset, host reset and firmware reset. no need to change this value for normal usage. apvol - audio playback volume register - (write 96h) bit 7 - 4: lvol[3:0] - left channel volume control bit 3:0: rvol[3:0] - right channel v olume control lvol3 - 0/rvol3 - 0 binary number attenuation (db) fh ~ ch ffh 0 (on) bh 80h - 6.00 ah 40h - 12.0 9h 20h - 18.0 8h ~ 5h 10h - 24.0 4h 08h - 30.0 3h 04h - 36.0 2h 02h - 42.1 1h 01h - 48.0 0h 00h mute (off)
preliminary/confidential subject to change without notice w88227f/W88227QD - 89 - 1999/10/1 rev: 0.70 apack - audio playback interrupt ack nowledge - (write 97h) writing any value to this register deactivates flag apib (01h.r2) and its corresponding interrupt. puctl - pull up resistor control register - (write 98h) this register is used to control the utilization of two pull - up resistors on io cells. default value is 0. bit 7 - 6: hip[1:0] - host interface pull - up control setting these two bits low control two pull - up resistors of host interface i/o cells respectively. if these two bits are both high, no pull - up resistors exist. note that d d7 is controlled by dd7upb (98h.1) separately, bit 5 - 4: uip[1:0] - microprocessor interface pull - up control setting these two bits low control two pull - up resistors of up interface i/o cells respectively. if these two bits are both high, no pull - up resist ors exist. bit 3 - 2: rip[1:0] - ram interface pull - up control setting these two bits low control two pull - up resistors of ram interface i/o cells respectively. if these two bits are both high, no pull - up resistors exist. bit 1: dd7upb - dd7 pull - up enable setting this bit low enable the internal pull - up resister on the pin dd7 . bit 0: apipb - audio playback interface pull - up control setting this bit low enable the internal pull - up of the audio - playback output pin, including alrck, abck and asd. sictl - si nk current control register - (write 99h) - obsolete bicctl - buffer independent correction control register - (read/write 9ah) this register is 0 after chip reset, host reset and firmware reset. bit 7: bicen - buffer independent correction enable if th is bit is high, the buffer - independent - correction (bic mode) is enabled. otherwise, the real - time - correction (rtc mode) is enabled. bit 6: atmsen - automatic mode switch if this bit is high, the decoder automatically change from disk - monitor mode to the p re - set buffer - mode after the target is found.
preliminary/confidential subject to change without notice w88227f/W88227QD - 90 - 1999/10/1 rev: 0.70 bit 5: blimen - buffer limit enable if blimen (9ah.5) is high, the buffering of dsp data stops when the condition defined by blims (9ah.4) is met. this function should be enabled if bicen (9ah.7) is set high. bit 4: blims - buffer limit source select if blims (9ah.4) is high, the buffering stop when bufc (9bh,r) reach buflim (9bh,w) . if blims (9ah.4) is low, the buffering stops when buffering block (internal) reach tbh/l (24h/25h,r) minus 1. bit 3 - 0: rclim[3: 0] - repeat correction limit if bicen (9ah.7) is high, these four bits specify the maximum number of repeat correction. buflim - buffer limit register - (write 9bh) this register is used as buffer limit when blims (9ah.4) is high. this register can b e set the buffer - ring size minus n , where n is larger than 1. this register is 0 after master reset and firmware reset. in normal operation, this register only needs to be set once after power - on. bufc - buffer counter - (read 9bh) this counter increm ents when a sector is buffered into external ram. if acmen (9ch.6) is high, bufc (9bh,r) decrements at the end of each data - in block transfer unless the value is zero. the value follows 0 is 0. the transfer of working area data should be implemented as l inear transfer to prevent extra decrement of this counter. if acmen (9ch.6) is high, bufc (9bh,r) minus n right after skipc (9eh) is set n . this function can be used to implement the cache - partial - hit event. if both blimen (9ah.5) and blims (9ah.4) is hi gh, the buffering stop when this count reaches buflim (9bh,w) . the value in bufc (9bh,r) may exceed buflim (9bh,w) by one. this counter is synchronized to tcc (9dh) whenever decen (0ah.w7) is low. this counter is 0 after master reset and firmware reset. acctl - automatic cache control register - (read/write 9ch) this register is 0 after chip reset, host reset and firmware reset. bit 7: atten - automatic transfer trigger enable the control bit adtt (17h.w2) is automatically set high if all the follo wing conditions are met: atten (9ch.7) is high tcc (9dh) is not zero ttc (9fh) is not zero
preliminary/confidential subject to change without notice w88227f/W88227QD - 91 - 1999/10/1 rev: 0.70 bit 6: acmen - automatic cache management enable if acmen (9ch.6) is high, the following functions are enabled: tbkh/l (25h/24h) increments at the end of each data - in block transfer tcc (9dh) and ttc (9fh) decrements at the end of each data - in block transfer tcc (9dh) minus n and tbkh/l (25h/24h) plus n right after skipc (9eh) is set n if acmen (9ch.6) is high and ttc (9fh) is not zero, the following functions are e xecuted when adtt (17h.w2) is triggered: mbc4 - 0 (12h.4 - 0) ? min{ atlim (9ch.4 - 0) , tcc (9dh) , ttc (9fh) } minus 1 atbhi/lo (35h/34h) ? (mbc4 - 0 + 1) (twch/l + 1) x 2 if stwcen (18h.3) is high registers skipc (9eh) and ttc (9fh) are stuck at 0 if acmen (9c h.6) is low. bit 5: tcincen - transfer cache increment enable when this bit is high, the tcc (9dh) increments at the end of edc - checking if there is no staerr (80h.r6) or hcei (80h.r0) error. this bit should be high if tcc (9dh) is used to implement ca che management. bit 4 - 0: atlim[4:0] - automatic transfer block limit if acmen (9ch.6) is high and tcc (9fh) is not zero, these five bits specify the maximum number of blocks that can be transferred to host in one trigger. the minimum limit is 1. setting 0 to these bits specify limit as 32 blocks. tcc - transfer cache counter - (read/write 9dh) this counter can be used to implement cache management if rmsri (5ch.0) is high. if tcincen (9ch.5) is high, tcc (9dh) increments at the end of edc - checking if t here is no staerr (80h.r6) or hcei (80h.r0) error. if acmen (9ch.6) is high, tcc (9dh) decrements at the end of each data - in block transfer unless the value is zero. the value follows 0 is 0. the transfer of working area data should be implemented as lin ear transfer to prevent extra decrement of this counter. if acmen (9ch.6) is high, tcc (9dh) minus n right after skipc (9eh) is set n . this function can be used to implement the cache - partial - hit event. this register is 0 after chip reset, host reset and firmware reset. this counter should be set 0 in cache - miss case. writing this register should be prevented when the decoder is on or the data - in transfer is in progress.
preliminary/confidential subject to change without notice w88227f/W88227QD - 92 - 1999/10/1 rev: 0.70 skipc - skip count - (read/write 9eh) this register is used as skip count to im plement a partial - hit event of transfer cache. if acmen (9ch.6) is high, the following functions are executed right after skipc (9eh) is set n : bufc (9bh,r) minus n tcc (9dh) minus n tbh/l (25h/24h) plus n skipc (9eh) minus n after execution of the above operations, the value in skipc (9eh) is 0. this register is 0 after chip reset, host reset and firmware reset. this register is stuck at 0 if acmen (9ch.6) is low. ttc - total transfer count - (read/write 9fh) this register is used as total transfer c ount. if acmen (9ch.6) is high, ttc (9fh) decrements at the end of each data - in block transfer unless the value is zero. the value follows 0 is 0. the following events are generated at the end of data - in transfer only if tcc (9fh) is zero: tendb (01h.r6 ) ? 0 automatic status complete sequence if ascen (18h.5) is enabled this register is 0 after chip reset, host reset and firmware reset. this register is stuck at 0 if acmen (9ch.6) is low.
preliminary/confidential subject to change without notice w88227f/W88227QD - 93 - 1999/10/1 rev: 0.70 2.3 up8032 function the up8032 architecture consists of a core cont roller surrounded by various registers, four general purpose i/o ports, 512 bytes of ram, three timer/counters, a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64 k data storage space. 2.3.1 data memory the up8032 can access up to 64k bytes of external data memory. this memory region is accessed by the movx instructions. if the addressed external ram bank is assigned to aux_ram, the movx instruction is directed to the on - chip aux_ram without aff ecting port 0 and 2. in addition, the up8032 has the standard 256 bytes of on - chip ram. this can be accessed either by direct addressing or by indirect addressing. there are also some special function registers (sfrs), which can only be accessed by dire ct addressing. 2.3.2 ram and aux_ram the size of internal data ram is 512x 8 bytes. it is divided into two banks: 256 bytes of ram and 256 bytes of aux_ram. ram 0 ~127 can be addressed directly and indirectly. address pointers are r0 and r1 of the selected reg ister bank. ram 128~255 can only be addressed indirectly. address pointers are r0 and r1 of the selected registers bank. aux_ram 0~255 is addressed indirectly as the same way as external data memory with the movx instruction if the following conditions ar e satisfied: 1. earam (chpcon.4) is set high and 2. dph or p2 equals to xrbank (8fh) notice that aux_ram can be allocated to address other than 0000h ~ 00ffh by setting xrbank (8fh) . address pointer are r0 and r1 of the selected register bank and dptr. the fol lowing is an example to show how to access aux_ram by movx instruction. mov chpcon, #10h ; set earam to 1. mov xrbank, #12h ; allocate aux_ram to address 1200h to 12ffh. mov dptr, #1234h ; address aux_ram with offset 34h mov a, #55h mov x @dptr,a ; access aux - ram if earom (chpcon.5) is set high, the aux_ram is programmed as aux_rom mode that can be fetched and executed like an internal rom .
preliminary/confidential subject to change without notice w88227f/W88227QD - 94 - 1999/10/1 rev: 0.70 80h ffh 0000h ffffh 80h 7fh 00h 64 k bytes external data memory indirect addressing ram direct & indirect addressing sfrs direct addressing ffh aux ram with movx 00h ffh ffh 80h 7fh 30h 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh 18h 17h 10h 0fh 08h 07h 00h 78 79 7a 7b 7c 7d 7e 7f 70 71 72 73 74 75 76 77 68 69 6a 6b 6c 6d 6e 6f 60 61 62 63 64 65 66 67 58 59 5a 5b 5c 50 51 52 53 54 5d 5e 5f 55 56 57 48 49 4a 4b 4c 4d 4e 4f 40 41 42 43 44 45 46 47 38 39 3a 3b 3c 3d 3e 3f 30 31 32 33 34 35 36 37 28 29 2a 2b 2c 2d 2e 2f 20 21 22 23 24 25 26 27 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 14 15 16 17 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 04 05 06 07 indirect ram direct ram bank 3 bank 2 bank 1 bank 0 bit addressable 20h - 2fh
preliminary/confidential subject to change without notice w88227f/W88227QD - 95 - 1999/10/1 rev: 0.70 2.3.3 aux_rom mode and up programming flash if ear om (chpcon.5) is set high, the aux_ram is programmed as aux_rom mode that can be fetched and executed like an internal rom . it can be used as a self - programming rom code source to program external flash memory. in this mode, the following pins are direct ly controlled by its corresponding registers to implement the flash programming function. pin name register function a7 - a0 sfrfal (c4h) flash low address up27 - up20 sfrfah (c5h) flash high address up07 - up00 sfrfd (c6h) flash data gpio2/dao/nfce ufce (sf rcn.2) flash chip enable psen ufoe (sfrcn.1) flash output enable gpio1/nfwe ufwe (sfrcn.0) flash write enable note 1: the control bits in sfrcn (c7h) should be set the inverse value of its corresponding pins. note 2: in the switch period from external f lash memory to aux_rom , the program counter will be reset to zero, and uc will fetch and execute the rom code from address 00h of aux_rom. because the up will prefetch the rom code before switch, for sake of the system operating smoothly, the instruction mov chpcon,earom should will be followed by the instruction nop to avoid the danger caused by compulsive pc reset . 2.3.4 special function register (sfr) the sfrs can be accessed only by direct addressing, while the on - chip ram can be accessed by either direct or indirect addressing. and the aux_ram is only accessed by movx instruction with selected external ram address range. address spaces 20h to 2fh to internal ram are bit - addressable and can be used by the boolean variable manipulation instructions. for exam ple, bit 0 of address 20h has a boolean address 00h, and bit 7 of address 2fh has a boolean address 7fh. the higher boolean addresses (80h - ffh) are mapped into the sfr address space. to determine a boolean address in a particular bit - addressable sfr, one can combine the higher 5 bits of the sfr address with 3 lower bits that specify the desired bit in the sfr.
preliminary/confidential subject to change without notice w88227f/W88227QD - 96 - 1999/10/1 rev: 0.70 special function registers (sfrs) f8 ff f0 +b chpenr f7 e8 ef e0 +acc e7 d8 df d0 +psw d7 c8 +t 2con rcap2l rcap2h tl2 th2 cf c0 sfral sfrah sfrfd sfrcn c7 b8 +ip chpcon bf b0 +p3 b7 a8 +ie af a0 +p2 a7 98 +scon sbuf 9f 90 +p1 97 88 +tcon tmod tl0 tl1 th0 th1 wkctl xrbank 8f 80 +p0 sp dpl dph pcon 87 note: 1.the sfrs marked with a plus sign(+) are both byte - and bit - addressable. 2. the text of sfr with bold type characters are extension function registers. wkctl (8eh) - wake up control register the chip enters power - down mode by setting pd (pcon.1) high,. in this mode, the crystal feedback loop between uxi and uxo is closed. this register controls the wake up mechanism. bit 7: eiwk - enable interrupt wake up if this bit is high, this chip wake s up from power - down mode on int0 or int1. bit 4: ehwk - enable host wake up if this bit is high, the chip wake up from power - down mode when: (1) srst is set high if hiiten (2eh,w7) is high, or (2) reception of device reset command (opcode 08h) if arsten (2fh.w3) is high.
preliminary/confidential subject to change without notice w88227f/W88227QD - 97 - 1999/10/1 rev: 0.70 bit 2 - 0: csc[2:0] - crystal stabilization counter these bits define the time needed to release the clock into the chip. dsc no. of clocks remrak 000b 176 001b 352 010b 704 011b 1408 default 100b 2816 101b 5632 110b 11264 111b 22528 xrbank (8fh) - aux_ram bank selection register aux_ram can be allocated to address start from ( n 0100h) by setting xrbank (8fh) as n . aux_ram is addressed indirectly as the same way as external data memory with the movx instruction if earam (chpcon.4) is set high and dph or p2 equals to xrbank (8fh) . chpcon (bfh) - chip control register the chpcon (bfh) is read only by default. you must write #87, #59h sequentially to chpenr (f6h) to enable the chpcon write attribute, and write any other value to chpenr disable chpcon writ e attribute. bit 7, 0: swrst - software reset setting both of these bits high forces the up to the initial conditions after master reset. bit 5: earom - enable aux_rom mode setting this bit high enables aux_rom mode. bit 4: earam - enable aux_ram mode sett ing this bit high enables aux_ram mode.
preliminary/confidential subject to change without notice w88227f/W88227QD - 98 - 1999/10/1 rev: 0.70 sfrfal (c4h) - flash low byte address register if earom (chpcon.5) is set high, the value of this register controls pin a7 - a0. sfrfah (c5h) - flash high byte address register if earom (chpcon.5) is set high, th e value of this register controls pin up27 - up20. sfrfd (c6h) - flash data register if earom (chpcon.5) is set high, this register controls and reflect the status of up07 - up00. sfrcn (c7h) - flash control register bit 2: ufce - flash chip enable if earo m (chpcon.5) is set high, the inverse status of this bit controls pin gpio2/dao/nfce. bit 1: ufoe - flash output enable if earom (chpcon.5) is set high, the inverse status of this bit controls pin psen. bit 0: ufwe - flash write enable if earom (chpcon.5) is set high, the inverse status of this bit controls pin gpio1/nfwe. chpenr (f6h) - chip control register write enable register the chpcon (bfh) is read only by default. you must write #87,#59h sequentially to chpenr (f6h) to enable the chpcon write att ribute, and write any other value to chpenr disable chpcon write attribute.
preliminary/confidential subject to change without notice w88227f/W88227QD - 99 - 1999/10/1 rev: 0.70 3. diagram of equivalent circuit in input/output port ? dxi/dxo and uxi/uxo ? npor, nhrst ? lrck, bck, sdata, c2po vss xoff control xoff to internal circuit xi xo input input data input input data schmitt vdd internal pull - up
preliminary/confidential subject to change without notice w88227f/W88227QD - 100 - 1999/10/1 rev: 0.70 ? scsd, wfck, scsyn ? nhrd, nhwr, ncs1, ncs3, da2 - 0, ndma ck ? nrsto, cko ? alrck, abck input input data schmitt input input data schmitt vdd internal pull - up pull - up enable output data output vdd output data output enable output internal pull - up pull - up enable
preliminary/confidential subject to change without notice w88227f/W88227QD - 101 - 1999/10/1 rev: 0.70 ? ncs16 ? hirq, iordy, dmarq, a7 - 0 ? gpio1 - 4, ra7 - 0, rd15 - 0, dd15 - 0, exck, asd/nroe vdd input data output data output enable input/ output internal pull - up pull - up enable schmitt output enable output vss vss output data output enable output
preliminary/confidential subject to change without notice w88227f/W88227QD - 102 - 1999/10/1 rev: 0.70 ? ndasp, npdiag ? p0 ? p1, p2, p3, psen vdd input data output enable input/ output internal pull - up pull - up enable schmitt vss vss input data output data output enable input/ output schmitt input data output data output enable input/ output schmitt vdd vdd
preliminary/confidential subject to change without notice w88227f/W88227QD - 103 - 1999/10/1 rev: 0.70 4. electronic characteristics 4.1 absolute maximum ratings sym parameter min max unit v dd power supply voltage - 0.3 6.5 v v in input voltage - 0.3 v dd + 0.3 v t op operation temperature 0 70 c t st storage temperature - 55 150 c 4.2 dc characteristics (t a = 0 c to 70 c, v dd = 5v 5%, v ss = 0v) sym parameter min max unit condition v oh output h igh voltage 2.4 v i oh =400 m a v ol output low voltage 0.4 v i ol (note 1) v ih1 input high voltage 0.7 v dd v dd +0.5 v dxi, uxi, lrck, v il1 input low voltage - 0.5 0.3 v dd v bck, sdata, c2po v ih2 input high voltage 2 v dd +0.5 v others v il2 input low voltage - 0.5 0.8 v i li1 (1) input leakage current - 140 - 400 m a i li2 (2) input leakage current - 80 - 200 m a i li3 (3) input leakage current - 40 - 100 m a i li4 (4) input leakage current - 10 - 40 m a pins with pull - up resistor at pad = 0v (notes 3) i li5 input leak age current - 10 10 m a others note (1): output current (iol) capabilities: 4ma: up10 - 17, up20 - 27, up30 - 37, a0 - 7 6ma: gpio1 - 4, cko, exck, ra7 - ra0, rd0 - 15, alrck, abck, asd 8ma: up00 - 07, cas, cash, ras, nwre 12ma: dd0 - 15, ndasp, npdiag, hirq, dmarq 24ma: ncs 16, iordy note (2): the chip contains internal resistance between uxi/uxo and dxi/dxo note (3): the chip contains internal pull - up resistance between vdd and the following pins: type (1): da0 - 2, nhrd, nhwr, ncs1, ncs3, ndmack, npor, nhrst, psen type (2): d d0 - 15, rd0 - 15, ndasp, npdiag, exck type (3): alrck, abck, asd, ra0 - 7, gpio1 - 4 type (4): up10 - 17, up20 - 27, up30 - 37, a7, a6
preliminary/confidential subject to change without notice w88227f/W88227QD - 104 - 1999/10/1 rev: 0.70 4.3 ac characteristics ? reset timing item symbol description min. (ns) max. (ns) notes 1 t rst reset pulse width 24 t up (1) note (1): t up = cycle time of uck (clock from pin uxi). npor nhrst t rst
preliminary/confidential subject to change without notice w88227f/W88227QD - 105 - 1999/10/1 rev: 0.70 ? up program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t up - d - - ns 4 address hold from ale low t aah 1 t up - d - - ns 1, 4 ale low to psen low t apl 1 t up - d - - n s 4 psen low to data valid t pda - - 2 t up ns 2 data hold after psen high t pdh 0 - 1 t up ns 3 data float after psen high t pdz 0 - 1 t up ns ale pulse width t alw 2 t up - d 2 t up - ns 4 psen pulse width t psw 3 t up - d 3 t up - ns 4 notes: 1. p 0.0 - p0.7, p2.0 - p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t up . 3. data have been latched internally prior to psen rise. 4. " d " (due to buffer driving delay and wire loading) is 20 ns. s1 uck s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale (internal) port 2 a0 - a7 a0 - a7 data a0 - a7 code t a0 - a7 data code port 0 psen pdh, t pdz t pdz t pda t pda t aah t aas t psw t apl t alw
preliminary/confidential subject to change without notice w88227f/W88227QD - 106 - 1999/10/1 rev: 0.70 ? up data read cycle parameter symb ol min. typ. max. unit notes ale low to up37 low t dar 3 t up - d - 3 t up+ d ns 1, 2 up37 low to data valid t dda - - 4 t up ns 1 data hold from up37 high t ddh 0 - 2 t up ns data float from up37 high t ddz 0 - 2 t up ns up37 pulse width t drd 6 t up - d 6 t up - ns 2 notes: 1. data memory access time is 8 t up . 2. " d " (due to buffer driving delay and wire loading) is 20 ns. s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 uck ale (internal) psen data a8 - a15 port 2 port 0 a0 - a7 up37 t ddh, t ddz t dda t drd t dar
preliminary/confidential subject to change without notice w88227f/W88227QD - 107 - 1999/10/1 rev: 0.70 ? up data write cycle item symbol min. typ. max. unit ale low to up36 low t daw 3 t up - d - 3 t up + d ns data valid to up36 lo w t dad 1 t up - d - - ns data hold from up36 high t dwd 1 t up - d - - ns up36 pulse width t dwr 6 t up - d 6 t up - ns note: " d " (due to buffer driving delay and wire loading) is 20 ns. s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 uck ale (internal) psen a8 - a15 data out port 2 port 0 a0 - a7 up36 t t daw dad t dwr t dwd
preliminary/confidential subject to change without notice w88227f/W88227QD - 108 - 1999/10/1 rev: 0.70 ? up port access cycle parameter symbol min. typ. max. unit port input s etup to ale low t pds 1 t up - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t up - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, si nce it provides a convenient reference. uck ale (internal) s5 s6 s1 data out t t port input t sample pda pdh pds
preliminary/confidential subject to change without notice w88227f/W88227QD - 109 - 1999/10/1 rev: 0.70 5. ordering instruction part no. package w88227f pqfp 128 W88227QD lqfp 128 6. how to read the top marking example: the top marking of w88227f inbond w88227f 904ab27039530 1st line: winbond logo 2nd line: the ty pe number: w88227f or W88227QD 3rd line: tracking code 904 a f 1 7039530 904 : packages made in '99, week 4 a : assembly house id; a means ase, s means spil b : ic revision; a means version a, b means version b 2 : wafers manufactured in winb ond fab 2 7039530 : wafer production series lot number
preliminary/confidential subject to change without notice w88227f/W88227QD - 110 - 1999/10/1 rev: 0.70 7. package dimension (w88227f, 128 - pin pqfp) 1.dimension d & e do not include interlead flash. 2.dimension b does not include dambar protrusion/intrusion. 3.controlling dimension : millimeter 4.general appearance spec. should be based on final visual inspection spec. note: 5.pcb layout please use the "mm". symbol b c d e h d h e l y 0 a a l 1 1 2 e 7 0 0.08 1.60 0.95 17.40 0.80 17.20 0.65 17.00 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 min nom max dimension in mm 0.20 0.15 19.90 20.00 20.10 23.00 23.20 23.40 0.35 0.45 0.003 0 0.063 0.037 0.685 0.031 0.677 0.025 0.669 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 max nom min dimension in inch 0.006 0.008 7 0.783 0.787 0.791 0.905 0.913 0.921 0.014 0.018 l l 1 detail f c e b 1 38 h d d 39 64 h e e 102 65 seating plane see detail f y a a 1 a 2 128 103
preliminary/confidential subject to change without notice w88227f/W88227QD - 111 - 1999/10/1 rev: 0.70 (W88227QD, 128 - pin lqfp) 0.08 0 7 0 0.003 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.40 14.10 0.20 0.23 1.45 1.60 14.00 1.40 13.90 0.10 0.13 1.35 0.05 0.008 0.009 0.057 0.063 0.055 0.016 0.556 0.551 0.547 0.004 0.005 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 l1 e 0.006 0.006 0.15 0.16 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 q 0.638 0.630 0.622 controlling dimension : millimeters d d e e b a2 a1 a l1 e c l y y y h h 1 128 q 32 33 64 65 96 97 0.15 0.006 a2
preliminary/confidential subject to change without notice w88227f/W88227QD - 112 - 1999/10/1 rev: 0.70 8. example temperature profile for infrared reflow 50 100 150 200 250 0 temperature ( j ) 175 - 183 j time(sec) ( the ir reflow chart is just for reference ) over 215 j 15 sec. max 2 j /sec 235 j max. >15sec >20sec max 2 j /sec

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